Merge branch 'main' into bus_wrapper

.gitignore

@@ -0,0 +1,8 @@
+exec/*
+!exec/executable.txt
+*.log.txt
+*.out.txt
+mips_cpu_harvard.vcd
+.DS_Store
+.DS_Store
+inputs/.DS_Store

MIPS.txt

@@ -1,60 +0,0 @@
-MIPS 32 bits
-
-== Bits, Bytes, Hex ==
--- 8 bits = 1 byte = 2 hex
--- 32 bits = 4 bytes = 8 hex
--- e.g. 00000000 00000000 00000000 00000000 -> 0x00000000
-
-== CPU ==
-inputs: 
--- manual MIPS assembly code -> instructions in binaries
--- C code -> compiled c program under mips -> disassemble binaries -> assembly code -> instruction in binaries
--- these binary instructions goes into instruction memory
-outputs:
--- output of the instructions
-errors:
--- ?????? how do we detect errors ??????
-
-== Submodules ==
--- ALU
--- Register File
--- Data Memory
--- Instruction Register
--- PC
--- Control Unit
-
-== Testbench ==
--- ????? not so sure yet ?????
-
-== Endianess ==
--- big endian: bytes are numbered starting with byte 0 at MSB
--- use -EB flag to ensure big endian
-
-== Instruction Access ==
--- PC (program counter): 32 bit register
--- PC is initialised to 0xBFC00000
--- PC changed as instructions are executed
--- IR = Mem[PC] -> instruction is fetched from data memory using data at the address given by program counter
-
-Address bus: CPU -> Memory
-Data bus: CPU <=> Memory
-
-== Register File ==
--- 32 general-purpose registers
-
-== Program Counter ==
--- PC is just a 32 bit register in which the value (address of instruction) get updated by other blocks
--- Controlled by PCSrc (for branching or regular increment by 4 bytes)
-
-== Questions ==
-Pseudo-instructions -> how to deal with them -> convert to actual instructions?
-Do we implement big-endian mips?
-What verilator could be useful for
-How would a testbench in c++ be helpful?
-Don't understand that part where we need to implement cache
-
-== Todo ==
-Testbench in c++
-Cache
-CPU stall cycle
-

exec/executable.txt

@@ -0,0 +1 @@
+A folder for executables

inputs/addiu/addiu-2.txt

@@ -0,0 +1,2 @@
+2442000A
+00000008

inputs/and.txt

@@ -1,4 +0,0 @@
-3404000A
-3405000F
-00851024
-00000008

inputs/and/and-1.ref.txt

@@ -0,0 +1 @@
+2290649224

inputs/and/and-1.txt

@@ -0,0 +1,6 @@
+3c05cccc 
+34A5cccc
+3c04aaaa
+3484aaaa
+00851024
+00000008

inputs/andi/andi-1.ref.txt

@@ -0,0 +1 @@
+34952

inputs/andi/andi-1.txt

@@ -0,0 +1,4 @@
+3c04aaaa
+3404aaaa
+3082cccc
+00000008

inputs/beq/beq-1.ref.txt

@@ -0,0 +1 @@
+1

inputs/beq/beq-2.ref.txt

@@ -0,0 +1 @@
+15

inputs/beq/beq-2.txt

@@ -0,0 +1,8 @@
+34040005
+34050005
+10850003
+34020005
+00000008
+00000000
+2442000A
+00000008

inputs/bgez/bgez-1.ref.txt

@@ -0,0 +1 @@
+1

inputs/bgez/bgez-2.txt

@@ -0,0 +1,7 @@
+34040003
+04810003
+00000000
+24420001
+00000000
+24420005
+00000008

inputs/bgezal/bgezal-1.ref.txt

@@ -0,0 +1 @@
+2

inputs/bgtz/bgtz-1.ref.txt

@@ -0,0 +1 @@
+1

inputs/blez/blez-1.ref.txt

@@ -0,0 +1 @@
+1

inputs/bltz/bltz-1.ref.txt

@@ -0,0 +1 @@
+1

inputs/bltz/bltz-1.txt

@@ -1,4 +1,4 @@
-3C05FFFF
+3C04FFFF
 04800003
 00000000
 00000008

inputs/bltzal/bltzal-1.ref.txt

@@ -0,0 +1 @@
+2

inputs/bltzal/bltzal-1.txt

@@ -1,8 +1,8 @@
-3C05FFFF
+3C04FFFF
 04900004
 00000000
 24420001
-00000000
 00000008
+00000000
 34020001
 03E00008

inputs/bne/bne-1.ref.txt

@@ -0,0 +1 @@
+1

inputs/div.txt

@@ -1,4 +0,0 @@
-34040004
-34050003
-0085001A
-00000008

inputs/div/div-1.ref.txt

@@ -0,0 +1 @@
+3

inputs/div/div-1.txt

@@ -0,0 +1,7 @@
+34040003
+34050009
+00A4001A
+00002010
+00002812
+00851021
+00000008

inputs/divu.txt

@@ -1,4 +0,0 @@
-34040004
-34050003
-0085001B
-00000008

inputs/divu/divu-1.ref.txt

@@ -0,0 +1 @@
+1073741824

inputs/divu/divu-1.txt

@@ -0,0 +1,7 @@
+3C048000
+34050002
+0085001B
+00002010
+00002812
+00851021
+00000008

inputs/ibrahimreference.txt

@@ -1,481 +0,0 @@
-===== ADDIU ==========
-int main(void) {
-    int a = -2147483648 + -32768 ;
-}
-
-ORI $4,$0,-2147483648
-ADDIU $2,$4,-32768
-JR $0
-
-//used to check for overflow 32768 is 2^15 which should 
-be sign extended. 21... is 2^31 
-
-
-register_v0 = 
-
-==========XORI	Bitwise exclusive or immediate=============
-
-int main(void) {
-    int a = 5 ^ 2;
-}
-
-ori $4,$0,5
-xori $2,$4,2
-jr $0
-
-register 0 = 7
-
-34040005
-38820002
-00000008
-
-convert to little endian
-
-////////
-
-====XOR	Bitwise exclusive or==========
-
-int main(void) {
-    int a = 5 ^ 2;
-}
-
-ori $4, $0, 5
-ori $5, $0, 2
-xor $2, $4, $5
-jr $0
-
-register 0 = 7
-
-34040005
-34050002
-00851026
-00000008
-
-convert to little endian
-
-////////
-
-========SW	Store word==============
-
-int main(void) {
-
-
-ori $4, $0, 5 
-ori $5, $0, 1
-sw $4, 1($5)
-jr $0
-
-register 0 = 5
-
-34040005
-34050001
-aca40001
-00000008
-
-
-=========== SUBU	Subtract unsigned ===========
-
-int main(void) {
-    int a = 5-3;
-}
-
-ori $4,$0,5
-ori $5,$0,3
-subu $2,$4,$5
-jr $0
-
-
-register_v0 = 2
-
-
-34040005
-34050003
-00851023
-00000008
-
-
-========= SRLV	Shift right logical variable ======
-
-
-int main(void) {
-    int a = 2;
-    int b = 16>>a;
-}
-
-ori $4,$0,2
-ori $5,$0,16
-srlv $2,$5,$4
-jr $0
-
-register 0 = 3
-
-34040002
-34050010
-//////
-//////
-
-===============  SRL	Shift right logical  ==============
-
-
-int main(void) {
-    int a = -2147483647>>2; #logical shift - should feed in 0s
-}
-
-ori $4,$0,-2147483647
-srl $2,$4,$2
-jr $0
-
-register 0 = 536870912 (2^29)
-
-34040001
-00041002
-00000008
-
-========== SRAV	Shift right arithmetic variable =======
-
-int main(void) {
-    int a = 2;
-    int b = -2147483647>>2; #arithemtic shift not logical - feed in 1s (sign extension)
-}
-
-ori $4, $0, 2
-ori $5,$0,-2147483647
-srav $2,$5,$4
-jr $0
-
-register 0 = -536870912 (first 3 bits high - rest low)
-
-34040002
-34050001
-////////
-///////
-
-====== SRA	Shift right arithmetic ==========
-
-int main(void) {
-    int a = -2147483647>>2; #arithemtic shift not logical - feed in 1s (sign extension)
-}
-
-
-ori $4,$0,-2147483647
-sra $2,$4,$2
-jr $0
-
-register 0 = -536870912 (first 3 bits high - rest low)
-
-34040001
-00041003
-00000008
-
-======= SLTU	Set on less than unsigned =====
-
-int main() {
-    int a = 10;
-    int b = 9;
-
-    max = a < b ? 1 : 0;
-
-    return max;
-}
-
-
-ori $4, $0, 10
-ori $5, $0, 9
-sltu $2, $4, $5
-jr $0
-
-register 0 = 0
-
-3404000a
-34050009
-0085102b
-00000008
-
-=========== SLTIU	Set on less than immediate unsigned ==================
-
-int main() {
-    int a = 10;
-
-    max = a < 9 ? 1 : 0;
-
-    return max;
-}
-
-
-ori $4, $0, 10
-sltiu $2, $4, 9
-jr $0
-
-register 0 = 0
-
-3404000a
-2c820009
-00000008
-
-======= SLTI	Set on less than immediate (signed) ========
-
-int main() {
-    int a = 10;
-
-    max = a < 9 ? 1 : 0;
-
-    return max;
-}
-
-
-ori $4, $0, 10
-slti $2, $4, 9
-jr $0
-
-register 0 = 0
-
-3404000a
-28820009
-00000008
-
-
-
-======= SLLV	Shift left logical variable ======
-
-
-int main(void) {
-    int a = 2;
-    int b = 3<<a;
-}
-
-ori $4,$0,2
-ori $5,$0,3
-sllv $2,$5,$4
-jr $0
-
-register 0 = 16
-
-34040002
-34050003
-//////
-//////
-
-
-======= SLL	Shift left logical  ======
-
-
-int main(void) {
-    int a = 3<<2;
-}
-
-ori $4,$0,3
-sll $2,$4,2
-jr $0
-
-register 0 = 16
-
-34040003
-00041080
-00000008
-
-======== SB	Store byte =======
-
-ori $4, $0, 1029
-ori $5, $0, 1
-sb $4, 1($5)
-jr $0
-
-register 0 = 5
-
-34040405
-34050001
-a0a40001
-00000008
-
- ======== ORI	Bitwise or immediate ===
-
-ori $4,$0,3
-jr $0
-
-register a0 = 3
-
-34040003
-00000008
-
-======== OR	Bitwise or  ===
-
-int main(){
-    int a =5;
-    int b= 3;
-
-    int c = 5 | 3;
-
-    return 0;
-}
-
-
-ori $4, $0, 5
-ori $5, $0, 3
-or $2, $4, $5
-jr $0
-
-
-34040005
-34050003
-00851025
-00000008
-
-register 0 = 7
-
-======= MULT	Multiply =====
-
-ori $4, $0, 4
-ori $5, $0, 3
-mult $4, $5
-jr $0
-
-$LO = 12
-
-34040004
-34050003
-00850018
-00000008
-
-
-======= MULT Multiply =====
-
-ori $4, $0, 4
-ori $5, $0, 3
-mult $4, $5
-mflo $2
-jr $0
-
-register v0 = 12
-
-34040004
-34050003
-00850018
-00001012
-00000008
-
-======= MULTU	Multiply unsigned =====
-
-ori $4, $0, 4
-ori $5, $0, 3
-multu $4, $5
-jr $0
-
-
-$LO = 12
-
-34040004
-34050003
-00850019
-00000008
-
-
-======= MULTU	Multiply unsigned =====
-
-ori $4, $0, 4
-ori $5, $0, 3
-multu $4, $5
-mflo $2
-jr $0
-
-
-$2 = 12
-
-34040004
-34050003
-00850019
-00001012
-00000008
-
-======= MFLO Move from lo ======
-
-ori $4, $0, 4
-ori $5, $0, 3
-multu $4, $5
-mflo $2
-jr $0
-
-
-$2 = 12
-
-34040004
-34050003
-00850019
-00001012
-00000008
-
-=========== MFHI Move from Hi ==========
-
-ori $4, $0, 3
-mthi $4
-mfhi $2
-jr $0
-
-register v0 = 3
-
-34040003
-00800011
-00001010
-00000008
-
-======== MTHI	Move to HI ====
-
-ori $4, $0, 5
-mthi $4
-jr $0
-
-
-$HI = 5
-
-34040005
-00800011
-00000008
-
-======= MTLO	Move to LO ===
-
-ori $4, $0, 5
-mtlo $4
-jr $0
-
-
-$HI = 5
-
-34040005
-00800013
-00000008
-
-==================== SH	Store half-word =======
-
-/////////
-
-
-======== DIV Divide  ======
-
-
-ori $4, $0, 4
-ori $5, $0, 3
-div $4, $5
-jr $0
-
-
-$LO = 1
-$HI = 1
-
-34040004
-34050003
-0085001A
-00000008
-
-========= DIVU Divide unsigned =====
-
-ori $4, $0, 4
-ori $5, $0, 3
-divu $4, $5
-jr $0
-
-$LO = 1
-$HI = 1
-
-34040004
-34050003
-0085001B
-00000008

inputs/j/j-1.ref.txt

@@ -0,0 +1 @@
+1

inputs/j/j-1.txt

@@ -1,4 +1,4 @@
-08000004
+0BF00004
 00000000
 00000008
 00000000

inputs/jal/jal-1.ref.txt

@@ -0,0 +1 @@
+2

inputs/jal/jal-1.txt

@@ -1,4 +1,4 @@
-0C000005
+0FF00005
 00000000
 24420001
 00000008

inputs/jalr/jalr-1.ref.txt

@@ -0,0 +1 @@
+2

inputs/jalr/jalr-1.txt

@@ -1,5 +1,5 @@
-3405001C
+3C05BFC0
-3C05BCF0
+34A5001C
 00A02009
 00000000
 24420001

inputs/jr.txt

@@ -1,7 +0,0 @@
-34050014
-3C05BCF0
-00A00008
-00000000
-00000008
-34020001
-00000008

inputs/jr/jr-1.ref.txt

@@ -0,0 +1 @@
+10

inputs/jr/jr-1.txt

@@ -0,0 +1,7 @@
+3C05BFC0
+34A50014
+00A00008
+00000000
+00000008
+3402000A
+00000008

inputs/jr/jr-2.ref.txt

@@ -0,0 +1 @@
+5

inputs/jr/jr-2.txt

@@ -1,2 +1,2 @@
-34040003
 00000008
+34020005

inputs/lb/lb-1.data.txt

@@ -0,0 +1,4 @@
+00000000
+00008A00
+00000000
+00000000

inputs/lb/lb-1.ref.txt

@@ -0,0 +1 @@
+4294967178

inputs/lb/lb-1.txt

@@ -0,0 +1,3 @@
+34041001
+80820005
+00000008

inputs/lbu/lbu-1.data.txt

@@ -0,0 +1,4 @@
+00000000
+008A0000
+00000000
+00000000

inputs/lbu/lbu-1.ref.txt

@@ -0,0 +1 @@
+138

inputs/lbu/lbu-1.txt

@@ -0,0 +1,3 @@
+34041002
+90820004
+00000008

inputs/lh/lh-1.data.txt

@@ -0,0 +1,4 @@
+00000000
+00008123
+00000000
+00000000

inputs/lh/lh-1.ref.txt

@@ -0,0 +1 @@
+4294934819

inputs/lh/lh-1.txt

@@ -0,0 +1,3 @@
+34041000
+84820004
+00000008

inputs/lhu/lhu-1.data.txt

@@ -0,0 +1,4 @@
+00000000
+00008123
+00000000
+00000000

inputs/lhu/lhu-1.ref.txt

@@ -0,0 +1 @@
+33059

inputs/lhu/lhu-1.txt

@@ -0,0 +1,3 @@
+34041000
+94820004
+00000008

inputs/lui/lui-1.ref.txt

@@ -0,0 +1 @@
+305419896

inputs/lui/lui-1.txt

@@ -0,0 +1,3 @@
+3C021234
+34425678
+00000008

inputs/lw/lw-1.data.txt

@@ -0,0 +1,4 @@
+00000000
+12345678
+00000000
+00000000

inputs/lw/lw-1.ref.txt

@@ -0,0 +1 @@
+305419896

inputs/lw/lw-1.txt

@@ -0,0 +1,3 @@
+34041002
+8C820002
+00000008

inputs/lwl/lwl-1.data.txt

@@ -0,0 +1,4 @@
+00000000
+AAAA1234
+00000000
+00000000

inputs/lwl/lwl-1.ref.txt

@@ -0,0 +1 @@
+305419896

inputs/lwl/lwl-1.txt

@@ -0,0 +1,4 @@
+34041001
+34025678
+88820003
+00000008

inputs/lwr/lwr-1.data.txt

@@ -0,0 +1,4 @@
+00000000
+5678AAAA
+00000000
+00000000

inputs/lwr/lwr-1.ref.txt

@@ -0,0 +1 @@
+305419896

inputs/lwr/lwr-1.txt

@@ -0,0 +1,4 @@
+3C021234
+34041002
+98820003
+00000008

inputs/mfhi.txt

@@ -1,4 +0,0 @@
-34040003
-00800011
-00001010
-00000008

inputs/mflo.txt

@@ -1,5 +0,0 @@
-34040004
-34050003
-00850019
-00001012
-00000008

inputs/mthi/mthi-1.ref.txt

@@ -0,0 +1 @@
+5

inputs/mthi/mthi-1.txt

@@ -1,3 +1,4 @@
 34040005
 00800011
+00001010
 00000008

inputs/mtlo/mtlo-1.ref.txt

@@ -0,0 +1 @@
+5

inputs/mtlo/mtlo-1.txt

@@ -1,3 +1,4 @@
 34040005
 00800013
+00001012
 00000008

inputs/mult/mult-1.ref.txt

@@ -0,0 +1 @@
+12

inputs/mult/mult-1.txt

@@ -2,4 +2,5 @@
 34050003
 00850018
 00001012
+00000000
 00000008

inputs/multcurrent.txt

@@ -1,4 +0,0 @@
-34040004
-34050003
-00850018
-00000008

inputs/multu/multu-1.ref.txt

@@ -0,0 +1 @@
+12

inputs/multucurrent.txt

@@ -1,4 +0,0 @@
-34040004
-34050003
-00850019
-00000008

inputs/or/or-1.ref.txt

@@ -0,0 +1 @@
+7

inputs/ori/ori-1.ref.txt

@@ -0,0 +1 @@
+7

inputs/ori/ori-1.txt

@@ -0,0 +1,3 @@
+34020003
+34420005
+00000008

inputs/ori/ori-2.ref.txt

@@ -0,0 +1 @@
+65535

inputs/ori/ori-2.txt

@@ -0,0 +1,4 @@
+3404FFFF
+34052134
+00851025
+00000008

inputs/sb.txt

@@ -1,4 +0,0 @@
-34040405
-34050001
-a0a40001
-00000008

inputs/sb/sb-1.ref.txt

@@ -0,0 +1 @@
+120

inputs/sb/sb-1.txt

@@ -0,0 +1,7 @@
+3C041234
+34045678
+3C05BFC0
+3405001C
+A0A40000
+80A20000
+00000008