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Fix sllv, srlv, srav to shift by A[4:0]

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This commit is contained in:
jl7719 2020-12-20 09:07:35 +00:00
parent 1458a6c619
commit d3dcd92a44
4 changed files with 6 additions and 6 deletions
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2
inputs/slti/slti-2.instr.txt
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@ -1,4 +1,4 @@
3C04FFFF 3C04FFFF
3404FFFE 3484FFFE
00000008 00000008
2882FFFF 2882FFFF

2
inputs/sltiu/sltiu-2.instr.txt
View file

@ -1,5 +1,5 @@
3C04FFFF 3C04FFFF
3404FFFE 3484FFFE
00000008 00000008
2c82FFFF 2c82FFFF

2
inputs/sltiu/sltiu-2.ref.txt
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@ -1 +1 @@
1 0

6
rtl/mips_cpu_alu.v
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@ -138,7 +138,7 @@ end
end end
SLLV: begin SLLV: begin
ALURes = B << A; ALURes = B << A[4:0];
end end
SRL: begin SRL: begin
@ -146,7 +146,7 @@ end
end end
SRLV: begin SRLV: begin
ALURes = B >> A; ALURes = B >> A[4:0];
end end
SRA: begin SRA: begin
@ -154,7 +154,7 @@ end
end end
SRAV: begin SRAV: begin
ALURes = $signed(B) >>> A; ALURes = $signed(B) >>> A[4:0];
end end
EQ: begin EQ: begin