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https://github.com/supleed2/ELEC50010-IAC-CW.git
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changed control for aluop and naming
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@ -43,46 +43,15 @@ Memtoreg:
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10: PC+4 output
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*/
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/*
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Aluop:
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0: r-type instructions
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1: <0
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-BLTZAL BLTZ
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2: >=0
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-BGEZAL BGEZ
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3: =0
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-BEQ
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4: =/=0
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-BNE
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5: <=0
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-BLEZ
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6: >0
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-BGTZ
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7: add
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-ADDIU
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-all load and store instructions
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8: slt (signed)
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-STLI
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9: slt (unsigned)
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-STLIU
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10: and
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-ANDI
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11: or
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-ORI
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12: xor
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-XORI
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*/
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//Commented signals represents dont care(x)
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module MIPS_Control_Harvard(
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module mips_cpu_control{
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input logic[5:0] Instr,
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input logic[5:0] Instr2,
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input logic[5:0] rt,
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output logic[1:0] Regdst,
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output logic Branch,
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output logic Memread,
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output logic[1:0] Memtoreg,
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output logic[3:0] Aluop,
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output logic Memwrite,
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output logic Alusrc,
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output logic Regwrite,
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@ -97,7 +66,6 @@ module MIPS_Control_Harvard(
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Memread=0;
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Memwrite=0;
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Memtoreg=2'b00;
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Aluop=4'd0;
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Alusrc=0;
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Regwrite=1;
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Jump=0;
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@ -107,16 +75,10 @@ module MIPS_Control_Harvard(
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Branch=1;
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Memread=0;
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Memwrite=0;
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if(Instr2[5]==1)begin
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if(rt[5]==1)begin
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Memtoreg=2'b10;
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Regwrite=1;
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end
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if (Instr2[0]==0)begin
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Aluop=4'd1;
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end
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if (Instr2[0]==1)begin
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Aluop=4'd2;
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end
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Alusrc=0;
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Jump=0;
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end
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@ -125,7 +87,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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//Memtoreg=;
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//Aluop=4'd;
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Memwrite=0;
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//Alusrc=;
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Regwrite=0;
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@ -136,7 +97,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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Memtoreg=2'b10;
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//aluop=4'd;
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Memwrite=0;
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//Alusrc=;
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Regwrite=1;
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@ -147,7 +107,6 @@ module MIPS_Control_Harvard(
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd3;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0;
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@ -158,7 +117,6 @@ module MIPS_Control_Harvard(
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd4;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0
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@ -169,7 +127,6 @@ module MIPS_Control_Harvard(
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd5;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0;
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@ -180,7 +137,6 @@ module MIPS_Control_Harvard(
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Aluop4'd6;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0;
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@ -191,7 +147,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -202,7 +157,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd8;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -213,7 +167,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd9;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -224,7 +177,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd10;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -235,7 +187,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd11;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -246,7 +197,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd12;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -257,7 +207,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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Memtoreg=2b'00;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -268,7 +217,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -279,7 +227,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd8;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -290,7 +237,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -301,7 +247,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -334,7 +277,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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@ -345,7 +287,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd7;
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Memwrite=1;
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Alusrc=1;
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Regwrite=0;
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@ -356,7 +297,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd7;
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Memwrite=1;
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Alusrc=1;
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Regwrite=0;
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@ -367,7 +307,6 @@ module MIPS_Control_Harvard(
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Branch=0;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd7;
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Memwrite=1;
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Alusrc=1;
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Regwrite=0;
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