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changed control for aluop and naming

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yhp19 2020-12-02 21:55:17 +08:00
parent 2a6d87c7b8
commit d1d64ae747
1 changed files with 3 additions and 64 deletions
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67
rtl/mips_cpu_control.v
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@ -43,46 +43,15 @@ Memtoreg:
10: PC+4 output 10: PC+4 output
*/ */
/*
Aluop:
0: r-type instructions
1: <0
-BLTZAL BLTZ
2: >=0
-BGEZAL BGEZ
3: =0
-BEQ
4: =/=0
-BNE
5: <=0
-BLEZ
6: >0
-BGTZ
7: add
-ADDIU
-all load and store instructions
8: slt (signed)
-STLI
9: slt (unsigned)
-STLIU
10: and
-ANDI
11: or
-ORI
12: xor
-XORI
*/
//Commented signals represents dont care(x) //Commented signals represents dont care(x)
module MIPS_Control_Harvard( module mips_cpu_control{
input logic[5:0] Instr, input logic[5:0] Instr,
input logic[5:0] Instr2, input logic[5:0] rt,
output logic[1:0] Regdst, output logic[1:0] Regdst,
output logic Branch, output logic Branch,
output logic Memread, output logic Memread,
output logic[1:0] Memtoreg, output logic[1:0] Memtoreg,
output logic[3:0] Aluop,
output logic Memwrite, output logic Memwrite,
output logic Alusrc, output logic Alusrc,
output logic Regwrite, output logic Regwrite,
@ -97,7 +66,6 @@ module MIPS_Control_Harvard(
Memread=0; Memread=0;
Memwrite=0; Memwrite=0;
Memtoreg=2'b00; Memtoreg=2'b00;
Aluop=4'd0;
Alusrc=0; Alusrc=0;
Regwrite=1; Regwrite=1;
Jump=0; Jump=0;
@ -107,16 +75,10 @@ module MIPS_Control_Harvard(
Branch=1; Branch=1;
Memread=0; Memread=0;
Memwrite=0; Memwrite=0;
if(Instr2[5]==1)begin if(rt[5]==1)begin
Memtoreg=2'b10; Memtoreg=2'b10;
Regwrite=1; Regwrite=1;
end end
if (Instr2[0]==0)begin
Aluop=4'd1;
end
if (Instr2[0]==1)begin
Aluop=4'd2;
end
Alusrc=0; Alusrc=0;
Jump=0; Jump=0;
end end
@ -125,7 +87,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
//Memtoreg=; //Memtoreg=;
//Aluop=4'd;
Memwrite=0; Memwrite=0;
//Alusrc=; //Alusrc=;
Regwrite=0; Regwrite=0;
@ -136,7 +97,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
Memtoreg=2'b10; Memtoreg=2'b10;
//aluop=4'd;
Memwrite=0; Memwrite=0;
//Alusrc=; //Alusrc=;
Regwrite=1; Regwrite=1;
@ -147,7 +107,6 @@ module MIPS_Control_Harvard(
Branch=1; Branch=1;
Memread=0; Memread=0;
//Memtoreg=; //Memtoreg=;
Aluop=4'd3;
Memwrite=0; Memwrite=0;
Alusrc=0; Alusrc=0;
Regwrite=0; Regwrite=0;
@ -158,7 +117,6 @@ module MIPS_Control_Harvard(
Branch=1; Branch=1;
Memread=0; Memread=0;
//Memtoreg=; //Memtoreg=;
Aluop=4'd4;
Memwrite=0; Memwrite=0;
Alusrc=0; Alusrc=0;
Regwrite=0 Regwrite=0
@ -169,7 +127,6 @@ module MIPS_Control_Harvard(
Branch=1; Branch=1;
Memread=0; Memread=0;
//Memtoreg=; //Memtoreg=;
Aluop=4'd5;
Memwrite=0; Memwrite=0;
Alusrc=0; Alusrc=0;
Regwrite=0; Regwrite=0;
@ -180,7 +137,6 @@ module MIPS_Control_Harvard(
Branch=1; Branch=1;
Memread=0; Memread=0;
//Memtoreg=; //Memtoreg=;
Aluop4'd6;
Memwrite=0; Memwrite=0;
Alusrc=0; Alusrc=0;
Regwrite=0; Regwrite=0;
@ -191,7 +147,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
Memtoreg=2'b00; Memtoreg=2'b00;
Aluop=4'd7;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -202,7 +157,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
Memtoreg=2'b00; Memtoreg=2'b00;
Aluop=4'd8;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -213,7 +167,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
Memtoreg=2'b00; Memtoreg=2'b00;
Aluop=4'd9;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -224,7 +177,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
Memtoreg=2'b00; Memtoreg=2'b00;
Aluop=4'd10;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -235,7 +187,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
Memtoreg=2'b00; Memtoreg=2'b00;
Aluop=4'd11;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -246,7 +197,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
Memtoreg=2'b00; Memtoreg=2'b00;
Aluop=4'd12;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -257,7 +207,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
Memtoreg=2b'00; Memtoreg=2b'00;
Aluop=4'd7;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -268,7 +217,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=1; Memread=1;
Memtoreg=2'b01; Memtoreg=2'b01;
Aluop=4'd7;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -279,7 +227,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=1; Memread=1;
Memtoreg=2'b01; Memtoreg=2'b01;
Aluop=4'd8;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -290,7 +237,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=1; Memread=1;
Memtoreg=2'b01; Memtoreg=2'b01;
Aluop=4'd7;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -301,7 +247,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=1; Memread=1;
Memtoreg=2'b01; Memtoreg=2'b01;
Aluop=4'd7;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -312,7 +257,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=1; Memread=1;
Memtoreg=2'b01; Memtoreg=2'b01;
Aluop=4'd7;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -323,7 +267,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=1; Memread=1;
Memtoreg=2'b01; Memtoreg=2'b01;
Aluop=4'd7;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -334,7 +277,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=1; Memread=1;
Memtoreg=2'b01; Memtoreg=2'b01;
Aluop=4'd7;
Memwrite=0; Memwrite=0;
Alusrc=1; Alusrc=1;
Regwrite=1; Regwrite=1;
@ -345,7 +287,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
//Memtoreg=; //Memtoreg=;
Aluop=4'd7;
Memwrite=1; Memwrite=1;
Alusrc=1; Alusrc=1;
Regwrite=0; Regwrite=0;
@ -356,7 +297,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
//Memtoreg=; //Memtoreg=;
Aluop=4'd7;
Memwrite=1; Memwrite=1;
Alusrc=1; Alusrc=1;
Regwrite=0; Regwrite=0;
@ -367,7 +307,6 @@ module MIPS_Control_Harvard(
Branch=0; Branch=0;
Memread=0; Memread=0;
//Memtoreg=; //Memtoreg=;
Aluop=4'd7;
Memwrite=1; Memwrite=1;
Alusrc=1; Alusrc=1;
Regwrite=0; Regwrite=0;