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Add missing end to if statement

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Aadi Desai 2020-12-16 13:54:01 -08:00
parent da0c9aba01
commit d17060b0a1
1 changed files with 1 additions and 0 deletions
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rtl/mips_cpu_bus_memory.v
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@ -75,6 +75,7 @@ always_ff @(posedge clk) begin
data_memory[{address-32'h00001000}>>2][7:0] <= writedata[7:0]; data_memory[{address-32'h00001000}>>2][7:0] <= writedata[7:0];
end end
waitrequest <= 1'b0; // end with setting waitrequest low waitrequest <= 1'b0; // end with setting waitrequest low
end
end else begin end else begin
waitrequest <= 1'bx; waitrequest <= 1'bx;
readdata <= 32'hxxxxxxxx; readdata <= 32'hxxxxxxxx;