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Fix overall w.r.t iverilog compiler error
This commit is contained in:
parent
a2bcf3ed1b
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83537
exec/mips_cpu_harvard_tb_addu
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83537
exec/mips_cpu_harvard_tb_addu
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File diff suppressed because one or more lines are too long
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@ -1,4 +1,4 @@
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350C0003
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34040003
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350D0005
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34050005
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018D5021
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00851021
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01000008
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00000008
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@ -20,10 +20,10 @@ ORI $5,$0,5
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ADDU $2,$4,$5
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ADDU $2,$4,$5
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JR $0
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JR $0
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350C0003
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34040003
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350D0005
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34050005
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018D5021
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00851021
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01000008
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00000008
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register_vo = 8
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register_vo = 8
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@ -1,11 +1,11 @@
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module mips_cpu_alu(
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module mips_cpu_alu(
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input signed logic[31:0] A, //Bus A - Input from the Readdata1 output from the reg file which corresponds to rs.
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input logic signed[31:0] A, //Bus A - Input from the Readdata1 output from the reg file which corresponds to rs.
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input signed logic[31:0] B, //Bus B - Input from the Readdata2 output from the reg file which corresponds to rt.
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input logic signed[31:0] B, //Bus B - Input from the Readdata2 output from the reg file which corresponds to rt.
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input logic[4:0] ALUOp, // 5-bit output from Control that tells the alu what operation to do from a list of 20 distinct alu operations(see below).
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input logic[4:0] ALUOp, // 5-bit output from Control that tells the alu what operation to do from a list of 20 distinct alu operations(see below).
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input logic[4:0] shamt, //5-bit input used to specify shift amount for shift operations. Taken directly from the R-type instruction (Non-Variable) or from
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input logic[4:0] shamt, //5-bit input used to specify shift amount for shift operations. Taken directly from the R-type instruction (Non-Variable) or from
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output logic ALUCond, //If a relevant condition is met, this output goes high(Active High). Note: Relevant as in related to current condition being tested.
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output logic ALUCond, //If a relevant condition is met, this output goes high(Active High). Note: Relevant as in related to current condition being tested.
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output signed logic[31:0] ALURes, // The ouput of the ALU
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output logic signed[31:0] ALURes // The ouput of the ALU
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);
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);
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/*
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/*
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@ -64,7 +64,7 @@ Alu Operations:
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Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming errors, as a result of enum implemetnation quirks.
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Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming errors, as a result of enum implemetnation quirks.
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assign ALUOps = ALUOp
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assign ALUOps = ALUOp;
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always_comb begin
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always_comb begin
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@ -88,43 +88,43 @@ assign ALUOps = ALUOp
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end
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end
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AND: begin
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AND: begin
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ALUOut = A & B;
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ALURes = A & B;
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end
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end
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OR: begin
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OR: begin
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ALUOut = A | B;
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ALURes = A | B;
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end
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end
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XOR: begin
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XOR: begin
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ALUOut = A^B;
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ALURes = A^B;
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end
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end
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SLL: begin
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SLL: begin
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ALUOut = B << shamt;
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ALURes = B << shamt;
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end
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end
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SLLV: begin
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SLLV: begin
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ALUOut = B << A;
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ALURes = B << A;
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end
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end
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SRL: begin
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SRL: begin
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ALUOut = B >> shamt;
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ALURes = B >> shamt;
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end
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end
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SRLV: begin
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SRLV: begin
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ALUOut = B >> A;
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ALURes = B >> A;
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end
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end
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SRA: begin
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SRA: begin
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ALUOut = B >>> shamt;
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ALURes = B >>> shamt;
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end
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end
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SRAV: begin
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SRAV: begin
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ALUOut = B >>> A;
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ALURes = B >>> A;
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end
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end
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EQ: begin
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EQ: begin
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if A == B begin
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if (A == B) begin
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ALUCond = 1;
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ALUCond = 1;
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end
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end
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else begin
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else begin
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@ -134,7 +134,7 @@ assign ALUOps = ALUOp
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end
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end
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LES: begin
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LES: begin
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if A < B begin
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if (A < B) begin
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ALUCond = 1;
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ALUCond = 1;
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end
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end
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else begin
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else begin
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@ -144,17 +144,7 @@ assign ALUOps = ALUOp
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end
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end
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LEQ: begin
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LEQ: begin
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if A <= B begin
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if (A <= B) begin
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ALUCond = 1;
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end
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else begin
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ALUCond = 0;
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end
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end
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LEQ: begin
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if A <= B begin
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ALUCond = 1;
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ALUCond = 1;
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end
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end
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else begin
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else begin
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@ -164,7 +154,7 @@ assign ALUOps = ALUOp
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end
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end
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GRT: begin
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GRT: begin
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if A > B begin
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if (A > B) begin
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ALUCond = 1;
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ALUCond = 1;
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end
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end
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else begin
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else begin
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@ -174,7 +164,7 @@ assign ALUOps = ALUOp
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end
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end
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GEQ: begin
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GEQ: begin
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if A >= B begin
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if (A >= B) begin
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ALUCond = 1;
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ALUCond = 1;
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end
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end
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else begin
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else begin
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@ -184,7 +174,7 @@ assign ALUOps = ALUOp
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end
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end
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NEQ: begin
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NEQ: begin
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if A != B begin
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if (A != B) begin
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ALUCond = 1;
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ALUCond = 1;
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end
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end
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else begin
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else begin
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@ -45,7 +45,7 @@ Memtoreg:
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//Commented signals represents dont care(x)
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//Commented signals represents dont care(x)
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module mips_cpu_control{
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module mips_cpu_control(
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input logic[5:0] Instr,
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input logic[5:0] Instr,
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input logic[5:0] rt,
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input logic[5:0] rt,
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output logic[1:0] Regdst,
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output logic[1:0] Regdst,
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@ -55,7 +55,7 @@ module mips_cpu_control{
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output logic Memwrite,
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output logic Memwrite,
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output logic Alusrc,
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output logic Alusrc,
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output logic Regwrite,
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output logic Regwrite,
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output logic Jump,
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output logic Jump
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);
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);
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always_comb begin
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always_comb begin
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@ -119,7 +119,7 @@ module mips_cpu_control{
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//Memtoreg=;
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//Memtoreg=;
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Memwrite=0;
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Memwrite=0;
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Alusrc=0;
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Alusrc=0;
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Regwrite=0
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Regwrite=0;
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Jump=0;
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Jump=0;
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end
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end
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6'd6: begin
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6'd6: begin
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@ -206,7 +206,7 @@ module mips_cpu_control{
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Regdst=2'b00;
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Regdst=2'b00;
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Branch=0;
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Branch=0;
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Memread=0;
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Memread=0;
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Memtoreg=2b'00;
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Memtoreg=2'b00;
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Memwrite=0;
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Memwrite=0;
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Alusrc=1;
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Alusrc=1;
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Regwrite=1;
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Regwrite=1;
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@ -23,13 +23,15 @@ module mips_cpu_harvard(
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//Control Flags
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//Control Flags
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logic Jump, Branch, ALUSrc, ALUZero, RegWrite;
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logic Jump, Branch, ALUSrc, ALUZero, RegWrite;
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logic[5:0] ALUOp = instr_readdata[31:26];
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logic[5:0] ALUOp = instr_readdata[31:26];
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logic[999999999999999999999999999999999999999999999999999999999999999999:0] ALUFlags;
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logic[30:0] ALUFlags; //Not sure if this is needed anymore
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logic[1:0] RegDst, MemtoReg;
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logic[1:0] RegDst, MemtoReg;
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//PC wires
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//PC wires
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logic[31:0] pc_curr;
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logic[31:0] pc_curr;
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logic[31:0] pc_next = Jump ? Jump_addr : PCSrc ? {pc_curr+4+{{14{instr_readdata[15]}}, instr_readdata[15:0], 2'b00}} : {pc_curr+4};
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logic[31:0] pc_curr_next = pc_curr + 3'd4; //Added due to compilation error
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logic[31:0] Jump_addr = {{pc_curr+4}[31:28], instr_readdata[25:0], 2'b00};
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logic[31:0] pc_delay; //Added due to compilation error
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logic[31:0] Jump_addr = {pc_curr_next[31:28], instr_readdata[25:0], 2'b00};
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logic[31:0] pc_next = Jump ? Jump_addr : PCSrc ? {pc_curr_next + {{14{instr_readdata[15]}}, instr_readdata[15:0], 2'b00}} : pc_curr_next;
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logic PCSrc = Branch && ALUZero;
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logic PCSrc = Branch && ALUZero;
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//Instruction MEM
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//Instruction MEM
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@ -54,7 +56,7 @@ assign data_address = ALUOut; //address to be written to comes from ALU
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assign data_writedata = read_data2; //data to be written comes from reg read bus 2
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assign data_writedata = read_data2; //data to be written comes from reg read bus 2
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//Writeback logic
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//Writeback logic
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logic[31:0] writeback = MemtoReg==2'b10 ? {pc_curr+4} : MemtoReg==2'b01 ? data_readdata : ALUOut;
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logic[31:0] writeback = MemtoReg==2'b10 ? {pc_curr_next} : MemtoReg==2'b01 ? data_readdata : ALUOut;
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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pc_delay <= pc_curr;
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pc_delay <= pc_curr;
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@ -67,16 +69,16 @@ pc pc(
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.pc_out(pc_curr)
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.pc_out(pc_curr)
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);
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);
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control control( //control flags block
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mips_cpu_control control( //control flags block
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.opcode(opcode), //opcode to be decoded
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.Instr(opcode), //opcode to be decoded
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.jump(Jump), //jump flag: 0 - increment or branch, 1 - J-type jump
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.Jump(Jump), //jump flag: 0 - increment or branch, 1 - J-type jump
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.branch(Branch), //branch flag: 0 - increment, 1 - branch if ALU.Zero == 1
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.Branch(Branch), //branch flag: 0 - increment, 1 - branch if ALU.Zero == 1
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.memread(data_read), //tells data memory to read out data at dMEM[ALUout]
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.Memread(data_read), //tells data memory to read out data at dMEM[ALUout]
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.memtoreg(MemtoReg), //0: writeback = ALUout, 1: writeback = data_readdata
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.Memtoreg(MemtoReg), //0: writeback = ALUout, 1: writeback = data_readdata
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.memwrite(data_write), //tells data memory to store data_writedata at data_writeaddress
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.Memwrite(data_write), //tells data memory to store data_writedata at data_writeaddress
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.alusrc(ALUSrc), //0: ALUin2 = read_data2, 1: ALUin2 = signextended(instr_readdata[15:0])
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.Alusrc(ALUSrc), //0: ALUin2 = read_data2, 1: ALUin2 = signextended(instr_readdata[15:0])
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.regwrite(RegWrite), //tells register file to write writeback to rd
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.Regwrite(RegWrite), //tells register file to write writeback to rd
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.regdst(RegDst) //select Rt, Rd or $ra to store to
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.Regdst(RegDst) //select Rt, Rd or $ra to store to
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);
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);
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regfile regfile(
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regfile regfile(
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@ -91,19 +93,20 @@ regfile regfile(
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.readdata2(read_data2), //read port 2 output
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.readdata2(read_data2), //read port 2 output
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.regv0(register_v0) //debug output of $v0 or $2 (first register for returning function results
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.regv0(register_v0) //debug output of $v0 or $2 (first register for returning function results
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);
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);
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/*
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alucontrol alucontrol(
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alucontrol alucontrol(
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.ALUOp(ALUOp), //opcode of instruction
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.ALUOp(ALUOp), //opcode of instruction
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.funct(immediate[5:0]), //funct of instruction
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.funct(immediate[5:0]), //funct of instruction
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.aluflags(ALUFlags) //ALU Control flags
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.aluflags(ALUFlags) //ALU Control flags
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);
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);
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*/
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alu alu(
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mips_cpu_alu alu(
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.ALUFlags(ALUFlags), //selects the operation carried out by the ALU
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//.ALUFlags(ALUFlags), //selects the operation carried out by the ALU
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.A(alu_in1), //operand 1
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.A(alu_in1), //operand 1
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.B(alu_in2), //operand 2
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.B(alu_in2), //operand 2
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.ALUzero(ALUZero), //is the result zero, used for checks
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.ALUCond(ALUZero), //is the result zero, used for checks
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.ALUOut(ALUOut), //output/result of operation
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.ALURes(ALUOut), //output/result of operation
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.shamt(shamt)
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.shamt(shamt),
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.ALUOp(ALUOp)
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);
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);
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endmodule : mips_cpu_harvard
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endmodule : mips_cpu_harvard
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@ -42,18 +42,20 @@ module mips_cpu_memory(
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//Load contents from file if specified
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//Load contents from file if specified
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if (RAM_INIT_FILE != "") begin
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if (RAM_INIT_FILE != "") begin
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$display("RAM : INIT : Loading RAM contents from %s", RAM_INIT_FILE);
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$display("RAM : INIT : Loading RAM contents from %s", RAM_INIT_FILE);
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$readmemh(RAM_INIT_FILE, memory[3217031168:0]);
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$readmemh(RAM_INIT_FILE, memory, 32'hBFC00000, 32'd0);
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end
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end
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end
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end
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//Combinatorial read path for data and instruction.
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//Combinatorial read path for data and instruction.
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if (clk == 1) begin
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always_comb begin
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assign data_readdata = data_read ? memory[data_address] : 16'hxxxx;
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if (clk == 1'd1) begin
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assign instr_readdata = memory[instr_address];
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data_readdata = data_read ? memory[data_address] : 16'hxxxx;
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instr_readdata = memory[instr_address];
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end
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end
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else begin
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else begin
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assign data_readdata = data_readdata;
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data_readdata = data_readdata;
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assign instr_readdata = instr_address;
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instr_readdata = instr_address;
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end
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end
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end
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@ -15,7 +15,7 @@ reg[31:0] memory [31:0]; //32 register slots, 32-bits wide
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initial begin
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initial begin
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integer i; //Initialise to zero by default
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integer i; //Initialise to zero by default
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for (i = 0; i < 31; i++) begin
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for (i = 0; i < 32; i++) begin
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memory[i] = 0;
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memory[i] = 0;
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end
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end
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end
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end
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@ -37,13 +37,21 @@ then
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done
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done
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else
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else
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echo "ELSE";
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echo ${INSTR};
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# Run Testcase File Of Specified Instruction
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# Run Testcase File Of Specified Instruction
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# iverilog -g 2012 \
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# Windows Iverilog with WSL
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#/mnt/c/Windows/System32/cmd.exe /C iverilog -g2012 \
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# -s mips_cpu_harvard_tb \
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# -s mips_cpu_harvard_tb \
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# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.hex.txt\" \
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# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
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# -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
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# -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
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# ${SRC}
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# ${SRC}
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# Linux Iverilog
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iverilog -g2012 \
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-s mips_cpu_harvard_tb \
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-P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
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-o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
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${SRC}
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fi
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fi
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#/mnt/c/Windows/System32/cmd.exe /C \ # need this to run verilog on windows
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#/mnt/c/Windows/System32/cmd.exe /C \ # need this to run verilog on windows
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@ -10,8 +10,30 @@ module mips_cpu_harvard_tb;
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logic data_read, data_write;
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logic data_read, data_write;
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logic[31:0] data_readdata, data_writedata, data_address;
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logic[31:0] data_readdata, data_writedata, data_address;
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||||||
mips_cpu_memory #(RAM_INIT_FILE) ramInst(clk, data_address, data_write, data_read, data_writedata, data_readdata, instr_address, instr_readdata);
|
mips_cpu_memory #(RAM_INIT_FILE) ramInst(
|
||||||
mips_cpu_harvard cpuInst(clk, reset, active, register_v0, clk_enable, instr_address, instr_readdata, data_address, data_write, data_read, data_writedata, data_readdata);
|
.clk(clk),
|
||||||
|
.data_address(data_address),
|
||||||
|
.data_write(data_write),
|
||||||
|
.data_read(data_read),
|
||||||
|
.data_writedata(data_writedata),
|
||||||
|
.data_readdata(data_readdata),
|
||||||
|
.instr_address(instr_address),
|
||||||
|
.instr_readdata(instr_readdata)
|
||||||
|
);
|
||||||
|
mips_cpu_harvard cpuInst(
|
||||||
|
.clk(clk),
|
||||||
|
.reset(reset),
|
||||||
|
.active(active),
|
||||||
|
.register_v0(register_v0),
|
||||||
|
.clk_enable(clk_enable),
|
||||||
|
.instr_address(instr_address),
|
||||||
|
.instr_readdata(instr_readdata),
|
||||||
|
.data_address(data_address),
|
||||||
|
.data_write(data_write),
|
||||||
|
.data_read(data_read),
|
||||||
|
.data_writedata(data_writedata),
|
||||||
|
.data_readdata(data_readdata)
|
||||||
|
);
|
||||||
|
|
||||||
// Generate clock
|
// Generate clock
|
||||||
initial begin
|
initial begin
|
||||||
|
@ -37,14 +59,15 @@ module mips_cpu_harvard_tb;
|
||||||
reset <= 0;
|
reset <= 0;
|
||||||
|
|
||||||
@(posedge clk);
|
@(posedge clk);
|
||||||
assert(running==1)
|
assert(active==1) // Is this assert still valid?
|
||||||
else $display("TB : CPU did not set running=1 after reset.");
|
else $display("TB : CPU did not set active=1 after reset.");
|
||||||
|
|
||||||
while (running) begin
|
while (active) begin
|
||||||
@(posedge clk);
|
@(posedge clk);
|
||||||
end
|
end
|
||||||
|
|
||||||
$display("TB : finished; running=0");
|
$display("TB : finished; running=0");
|
||||||
|
$display("%d",register_v0);
|
||||||
$finish;
|
$finish;
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
Loading…
Reference in a new issue