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Added ALUZero Output + corrected other syntax errors

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Ibrahim 2020-12-02 13:12:48 +00:00
parent 89abb5c1ed
commit c4cae70ffc
1 changed files with 142 additions and 130 deletions
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266
rtl/mips_cpu_alu.v
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@ -13,7 +13,7 @@ module mips_cpu_alu(
reg [31:0] SignExtend, ZeroExtend; reg [31:0] SignExtend, ZeroExtend;
input logic[10:6] shamt = instr_readdata[10:6]; input logic[10:6] shamt = instr_readdata[10:6]
); );
@ -73,168 +73,180 @@ module mips_cpu_alu(
/* This is how I believe our ctrl flags should be arranged */ /* This is how I believe our ctrl flags should be arranged */
typedef enum logic [6:0]{ typedef enum logic [6:0]{
} ALUFlags; } ALUFlags;
always @(alu_in1, alu_in2, ALUFlags) always @(A,B, ALUFlags)
begin begin
SignExtend = {{16{immediate[15]}}, immediate}; SignExtend = {{16{immediate[15]}}, immediate};
ZeroExtend = {{16{1'b0}}, immediate}; ZeroExtend = {{16{1'b0}}, immediate};
case(ALUFlags) case(ALUFlags)
ADD: begin ADD: begin
ALUOut = A + B; // is it = or <= ?? ALUOut = A + B; // is it = or <= ??
end end
SUB: begin SUB: begin
ALUOut = A - B; ALUOut = A - B;
end end
MULT: begin MULT: begin
ALUOut = A * B; ALUOut = A * B;
end end
DIV: begin DIV: begin
ALUOut = A / B; ALUOut = A / B;
end end
XOR: begin XOR: begin
ALUOut = A^B; ALUOut = A^B;
end end
OR: begin OR: begin
ALUOut = A | B; ALUOut = A | B;
end end
SLL: begin SLL: begin
ALUOut = B << shamt //Shamt is instruction read data [10:6] ALUOut = B << shamt //Shamt is instruction read data [10:6]
end end
SRL: begin SRL: begin
ALUOut = B >> shamt //Shamt is instruction read data [10:6] ALUOut = B >> shamt //Shamt is instruction read data [10:6]
end end
SLLV: begin SLLV: begin
ALUOut = B << A ALUOut = B << A
end end
SRLV: begin SRLV: begin
ALUOut = B >> A ALUOut = B >> A
end end
AND: begin AND: begin
ALUOut = A & B; ALUOut = A & B;
end end
BEQ: begin BEQ: begin
if A = B begin if A = B begin
ALUOut = 0;
end
else begin
ALUOut;
end
end
BGEZ: begin
if A>=0 begin
ALUOut = 0; ALUOut = 0;
end end
else begin else begin
ALUOut; ALUOut;
end end
end
BGEZAL: begin end
if A>=0 begin
ALUOut = 0;
end
else begin
ALUOut;
end
end
BGTZ: begin BGEZ: begin
if A>0 begin if A>=0 begin
ALUOut = 0; ALUOut = 0;
end end
else begin else begin
AlUOut; ALUOut;
end end
end end
BGEZAL: begin
if A>=0 begin
ALUOut = 0;
end
else begin
ALUOut;
end
end
BGTZ: begin
if A>0 begin
ALUOut = 0;
end
else begin
AlUOut;
end
end
BLEZ: begin BLEZ: begin
if A<=0 begin if A<=0 begin
ALUOut = 0; ALUOut = 0;
end end
else begin else begin
AlUOut; AlUOut;
end end
end end
BNE: begin BNE: begin
if A<=0 begin if A<=0 begin
ALUOut = 0; ALUOut = 0;
end end
else begin else begin
AlUOut; AlUOut;
end end
end end
LB: begin LB: begin
ALUOut = A + SignExtend ALUOut = A + SignExtend
end end
LBU: begin LBU: begin
ALUOut = A + ZeroExtend ALUOut = A + ZeroExtend
end end
LH: begin LH: begin
ALUOut = A + SignExtend ALUOut = A + SignExtend
end end
LHU: begin LHU: begin
ALUOut = A + ZeroExtend ALUOut = A + ZeroExtend
end end
LUI: begin LUI: begin
ALUOut = {immediate, {16{1'b0}}}; ALUOut = {immediate, {16{1'b0}}};
end end
SB: begin SB: begin
ALUOut = A + SignExtend ALUOut = A + SignExtend
end end
SH: begin SH: begin
ALUOut = A + SignExtend ALUOut = A + SignExtend
end end
SLT: begin SLT: begin
ALUOut = $signed(A) < $signed(B) ? 1 : 0; ALUOut = $signed(A) < $signed(B) ? 1 : 0;
end end
SLTU: begin SLTU: begin
ALUOut = A < B ? 1 : 0; ALUOut = A < B ? 1 : 0;
end end
SRA: begin SRA: begin
ALUOut = $signed($signed(B) >>> shamt); ALUOut = $signed($signed(B) >>> shamt);
end end
SRAV: begin SRAV: begin
ALUOut = $signed($signed(B) >>> A); ALUOut = $signed($signed(B) >>> A);
end end
SW: begin SW: begin
ALUOut = A + SignExtend ALUOut = A + SignExtend
end end
end endcase
end
always @(ALUOut) begin
if (ALUOut == 0) begin
ALUZero <= 1;
end else begin
ALUZero <= 0;
end
end
end
endmodule endmodule