More testcases, testing, debugging

inputs/j.ref.txt

@@ -0,0 +1 @@
+1

inputs/jal.ref.txt

@@ -0,0 +1 @@
+2

inputs/jalr.ref.txt

@@ -0,0 +1 @@
+2

inputs/jr.ref.txt

@@ -0,0 +1 @@
+1

inputs/lb.data.txt

@@ -0,0 +1,4 @@
+00000000
+008A0000
+00000000
+00000000

inputs/lb.ref.txt

@@ -0,0 +1 @@
+4294967178

inputs/lb.txt

@@ -0,0 +1,3 @@
+34041003
+80820003
+00000008

inputs/lbu.data.txt

@@ -0,0 +1,4 @@
+00000000
+008A0000
+00000000
+00000000

inputs/lbu.ref.txt

@@ -0,0 +1 @@
+138

inputs/lbu.txt

@@ -0,0 +1,3 @@
+34041003
+90820003
+00000008

inputs/lh.data.txt

@@ -0,0 +1,4 @@
+00000000
+00008123
+00000000
+00000000

inputs/lh.ref.txt

@@ -0,0 +1 @@
+4294934819

inputs/lh.txt

@@ -0,0 +1,3 @@
+34041003
+84820004
+00000008

inputs/lhu.data.txt

@@ -0,0 +1,4 @@
+00000000
+00008123
+00000000
+00000000

inputs/lhu.ref.txt

@@ -0,0 +1 @@
+33059

inputs/lhu.txt

@@ -0,0 +1,3 @@
+34041003
+94820004
+00000008

inputs/lui.ref.txt

@@ -0,0 +1 @@
+305419896

inputs/lui.txt

@@ -0,0 +1,3 @@
+34045678
+3C021234
+00000008

inputs/lw.data.txt

@@ -0,0 +1,4 @@
+00000000
+12345678
+00000000
+00000000

inputs/lw.ref.txt

@@ -0,0 +1 @@
+305419896

inputs/lw.txt

@@ -0,0 +1,3 @@
+34041002
+8C820002
+00000008

inputs/lwl.data.txt

@@ -0,0 +1,4 @@
+00000000
+AAAA1234
+00000000
+00000000

inputs/lwl.ref.txt

@@ -0,0 +1 @@
+305419896

inputs/lwl.txt

@@ -0,0 +1,4 @@
+34041003
+34025678
+88820003
+00000008

inputs/lwr.data.txt

@@ -0,0 +1,4 @@
+00000000
+5678AAAA
+00000000
+00000000

inputs/lwr.ref.txt

@@ -0,0 +1 @@
+305419896

inputs/lwr.txt

@@ -0,0 +1,4 @@
+34041003
+3C021234
+98820002
+00000008

inputs/reference.txt

@@ -1,224 +0,0 @@
-== Instruction ==
-C code
-Assembly code
-Hex code
-Reference Output
-================
-
-== ADDIU Add immediate unsigned (no overflow) ==
-
-
-
-== ADDU Add unsigned (no overflow) ==
-
-int main(void) {
-    int a = 3 + 5;
-}
-
-ORI $4,$0,3
-ORI $5,$0,5
-ADDU $2,$4,$5
-JR $0
-
-34040003
-34050005
-00851021
-00000008
-
-register_v0 = 8
-
-
-== AND Bitwise and ==
-
-ANDI Bitwise and immediate
-
-==BEQ	Branch on equal==
-
-ORI $4,$0,5
-ORI $5,$0,5
-BEQ $4,$5,2
-ADDIU $6,$6,0 
-JR $0
-ORI $2,$0,1
-JR $0
-
-50004043
-50005043
-20005801
-00006C42
-80000000
-10002043
-80000000
-
-register_v0 = 1
-
-
-==BGEZ Branch on greater than or equal to zero==
-
-ORI $4,$0,3
-BGEZ $4,2
-ADDIU $6,$6,0
-JR $0
-ORI $2,$0,1
-JR $0
-
-30004043
-20001840
-00006C42
-80000000
-10002043
-80000000
-
-register_v0 = 1
-
-==BGEZAL Branch on non-negative (>=0) and link==
-
-ORI $4,$0,3
-BGEZAL $4,3
-ADDIU $6,$6,0
-ADDIU $2,$2,1
-JR $0
-ORI $2,$0,1
-JR $31
-
-30004043
-30001940
-00006C42
-10002442
-80000000
-10002043
-80000000
-
-register_v0 = 2
-
-
-==BGTZ Branch on greater than zero==
-
-ORI $4,$0,3
-BGTZ $4,2
-ADDIU $6,$6,0
-JR $0
-ORI $2,$0,1
-JR $0
-
-30004043
-200008C1
-00006C42
-80000000
-10002043
-80000000
-
-register_v0 = 1
-
-==BLEZ Branch on less than or equal to zero==
-
-ORI $4,$0,-1
-BLEZ $4,2
-ADDIU $6,$6,0
-JR $0
-ORI $2,$0,1
-JR $0
-
-FFFF4043
-20000881
-00006C42
-80000000
-10002043
-80000000
-
-register_v0 = 1
-
-==BLTZ Branch on less than zero==
-
-ORI $4,$0,-1
-BLTZ $4,2
-ADDIU $6,$6,0
-JR $0
-ORI $2,$0,1
-JR $0
-
-FFFF4043
-20000840
-00006C42
-80000000
-10002043
-80000000
-
-register_v0 = 1
-
-==BLTZAL	Branch on less than zero and link==
-
-ORI $4,$0,-1
-BLTZAL $4,3
-ADDIU $6,$6,0
-ADDIU $2,$2,1
-JR $0
-ORI $2,$0,1
-JR $31
-
-FFFF4043
-20000940
-00006C42
-10002442
-80000000
-10002043
-80000000
-
-register_v0 = 2
-
-==BNE	Branch on not equal==
-
-ORI $4,$0,3
-ORI $5,$0,5
-BNE $4,$5,2
-ADDIU $6, $6, 0
-JR $0
-ORI $2,$0,1
-JR $
-
-30004043
-50005043
-20005841
-00006C42
-80000000
-10002043
-80000000
-
-register_v0 = 1
-
-DIV	Divide
-DIVU	Divide unsigned
-J	Jump
-JALR	Jump and link register
-JAL	Jump and link
-JR	Jump register
-LB	Load byte
-LBU	Load byte unsigned
-LH	Load half-word
-LHU	Load half-word unsigned
-LUI	Load upper immediate
-LW	Load word
-LWL	Load word left
-LWR	Load word right
-MTHI	Move to HI
-MTLO	Move to LO
-MULT	Multiply
-MULTU	Multiply unsigned
-OR	Bitwise or
-ORI	Bitwise or immediate
-SB	Store byte
-SH	Store half-word
-SLL	Shift left logical
-SLLV	Shift left logical variable
-SLT	Set on less than (signed)
-SLTI	Set on less than immediate (signed)
-SLTIU	Set on less than immediate unsigned
-SLTU	Set on less than unsigned
-SRA	Shift right arithmetic
-SRAV	Shift right arithmetic
-SRL	Shift right logical
-SRLV	Shift right logical variable
-SUBU	Subtract unsigned
-SW	Store word
-XOR	Bitwise exclusive or
-XORI	Bitwise exclusive or immediate

inputs/reference/ibrahimreference.txt

@@ -267,7 +267,7 @@ ori $4,$0,3
 sll $2,$4,2
 jr $0
 
-register 0 = 12
+register 0 = 16
 
 34040003
 00041080

inputs/reference/reference.txt

@@ -0,0 +1,564 @@
+== Instruction ==
+C code
+Assembly code
+Hex code
+Reference Output
+================
+
+ADDIU Add immediate unsigned (no overflow) 
+
+== ADDU Add unsigned (no overflow) ==
+
+int main(void) {
+    int a = 3 + 5;
+}
+
+ORI $4,$0,3
+ORI $5,$0,5
+ADDU $2,$4,$5
+JR $0
+
+34040003
+34050005
+00851021
+00000008
+
+register_v0 = 8
+
+==AND Bitwise and==
+
+ORI $5,$0,0xCCCC
+LUI $5,0xCCCC 
+ORI $4,$0,0xAAAA
+LUI $4,0xAAAA  
+AND  $2,$4,$5
+JR $0
+
+3405cccc
+3c05cccc
+3404aaaa
+3c04aaaa
+00851024
+00000008
+
+register_v0 = 0x88888888
+
+==ANDI Bitwise and immediate==
+
+ORI $4,$0,0xAAAA
+LUI $4,0xAAAA  
+ANDI $2,$4,0xCCCC
+JR $0
+
+3404aaaa
+3c04aaaa
+3082cccc
+00000008
+
+register_v0 = 0x00008888
+
+==BEQ	Branch on equal==
+
+ORI $4,$0,5
+ORI $5,$0,5
+BEQ $4,$5,3
+NOP 
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34040005
+34050005
+10850003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BGEZ Branch on greater than or equal to zero==
+
+ORI $4,$0,3
+BGEZ $4,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34040003
+04810003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BGEZAL Branch on non-negative (>=0) and link==
+
+ORI $4,$0,3
+BGEZAL $4,4
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $31
+
+34040003
+04910004
+00000000
+24420001
+00000008
+00000000
+34020001
+03E00008
+
+register_v0 = 2
+
+==BGTZ Branch on greater than zero==
+
+ORI $4,$0,3
+BGTZ $4,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34040003
+1C800003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BLEZ Branch on less than or equal to zero==
+
+LUI $4,0xFFFF
+BLEZ $4,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+3C05FFFF
+18800003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BLTZ Branch on less than zero==
+
+LUI $4,0xFFFF 
+BLTZ $4,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+3C05FFFF
+04800003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BLTZAL	Branch on less than zero and link==
+
+LUI $4,0xFFFF 
+BLTZAL $4,4
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $31
+
+3C05FFFF
+04900004
+00000000
+24420001
+00000000
+00000008
+34020001
+03E00008
+
+register_v0 = 2
+
+==BNE	Branch on not equal==
+
+ORI $4,$0,3
+ORI $5,$0,5
+BNE $4,$5,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34040003
+34040005
+14850003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==DIV	Divide== //May need other testcases for -ve/+ve, -ve/-ve
+
+ORI $4,$0,3
+ORI $5,$0,9
+DIV  $5,$4
+MFHI $4
+MFLO $5
+ADDU $2,$4,$5
+JR $0
+
+34040003
+34050009
+00A4001A
+00002010
+00002812
+00851021
+00000008
+
+register_v0 = 3
+
+==DIVU	Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve
+
+LUI $4,0x8000 
+ORI $5,$0,2
+DIVU  $4,$5
+MFHI $4
+MFLO $5
+ADDU $2,$4,$5
+JR $0
+
+34048000
+34050002
+0085001B
+00002010
+00002812
+00851021
+00000008
+
+register_v0 = 0x40000000
+
+==J	Jump==
+
+J 4
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+08000004
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==JALR	Jump and link register==
+
+ORI $5,$0,0x001C
+LUI $5,0xBFC0
+JALR $4,$5
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $4
+
+3405001C
+3C05BCF0
+00A02009
+00000000
+24420001
+00000008
+00000000
+34020001
+00800008
+
+register_v0 = 2
+
+==JAL	Jump and link==
+
+JAL 5
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $31
+
+0C000005
+00000000
+24420001
+00000008
+00000000
+34020001
+03E00008
+
+register_v0 = 2
+
+==JR	Jump register==
+
+ORI $5,$0,0x0014
+LUI $5,0xBFC0  
+JR $5  
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34050014
+3C05BCF0
+00A00008
+00000000
+00000008
+34020001
+00000008
+
+register_v0 = 1
+
+==LB	Load byte==
+
+ORI $4,$0,0x1003
+LB  $2,3($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+80820003
+00000008
+
+-Memory Hex
+
+00000000
+008A0000
+00000000
+00000000
+
+register_v0 = 0xFFFFFF8A
+
+==LBU	Load byte unsigned==
+
+ORI $4,$0,0x1003
+LBU  $2,3($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+90820003
+00000008
+
+-Memory Hex
+
+00000000
+008A0000
+00000000
+00000000
+
+register_v0 = 0x0000008A
+
+==LH	Load half-word==
+
+ORI $4,$0,0x1003
+LH  $2,4($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+84820004
+00000008
+
+-Memory Hex
+
+00000000
+00008123
+00000000
+00000000
+
+register_v0 = 0xFFFF8123
+
+==LHU	Load half-word unsigned==
+
+ORI $4,$0,0x1003
+LHU $2,4($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+94820004
+00000008
+
+-Memory Hex
+
+00000000
+00008123
+00000000
+00000000
+
+register_v0 = 0x00008123
+
+==LUI	Load upper immediate==
+
+ORI $2,$0,0x5678
+LUI $2,0x1234
+JR $0
+
+34045678
+3C021234
+00000008
+
+register_v0 = 0x12345678
+
+==LW	Load word==
+
+ORI $4,$0,0x1002
+LW  $2, 2($4)
+JR $0
+
+-Instruction Hex
+
+34041002
+8C820002
+00000008
+
+-Memory Hex
+
+00000000
+12345678
+00000000
+00000000
+
+register_v0 = 0x12345678
+
+==LWL	Load word left==
+
+ORI $4,$0,0x1003
+ORI $2,$0,0x5678
+LWL  $2,3($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+34025678
+88820003
+00000008
+
+-Memory Hex
+
+00000000
+AAAA1234
+00000000
+00000000
+
+register_v0 = 0x12345678
+
+==LWR	Load word right==
+
+ORI $4,$0,0x1003
+LUI $2,0x1234
+LWR $2,2($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+3C021234
+98820002
+00000008
+
+-Memory Hex
+
+00000000
+5678AAAA
+00000000
+00000000
+
+register_v0 = 0x12345678
+
+// DIVU Divide unsigned
+
+// DIV Divide
+
+//MFHI Move from Hi 
+
+//MFLO Move from lo 
+
+//MTHI	Move to HI
+
+//MTLO	Move to LO
+
+//MULT	Multiply**
+
+//MULTU	Multiply unsigned**
+
+//OR	Bitwise or
+
+//ORI	Bitwise or immediate
+
+//SB	Store byte
+
+//SH	Store half-word**
+
+//SLL	Shift left logical
+
+//SLLV	Shift left logical variable **
+
+//SLT	Set on less than (signed)
+
+//SLTI	Set on less than immediate (signed)
+
+//SLTIU	Set on less than immediate unsigned
+
+//SLTU	Set on less than unsigned
+
+//SRA	Shift right arithmetic
+
+//SRAV	Shift right arithmetic**
+
+//SRL	Shift right logical
+
+//SRLV	Shift right logical variable**
+
+//SUBU	Subtract unsigned
+
+//SW	Store word
+
+//XOR	Bitwise exclusive or
+
+//XORI	Bitwise exclusive or immediate

inputs/sll.ref.txt

@@ -1 +1 @@
-16
+12

inputs/srl.ref.txt

@@ -1 +1 @@
-8
+4

inputs/srl.txt

@@ -1,3 +1,3 @@
 34040010
-00041002
+00041082
 00000008

inputs/temp.ref.txt

@@ -1 +1 @@
-59
+8

inputs/temp.txt

@@ -1,5 +1,5 @@
-34020008
 00000008
+34020008
 00000000
 00000000
 00000000

rtl/mips_cpu_control.v

@@ -83,7 +83,6 @@ assign rt = Instr[20:16];
 
 always @(*) begin
     //CtrlRegDst logic
-    $display("Opcode: %h", op);
     if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI))begin
         CtrlRegDst = 2'd0; //Write address comes from rt
         $display("CTRLREGDST: Rt");
@@ -100,7 +99,7 @@ always @(*) begin
         CtrlPC = 2'd1; // Branches - Jumps relative to PC
     end else if((op==J) || (op==JAL))begin
         CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
-    end else if((funct==JR) || (funct==JALR))begin
+    end else if((op==SPECIAL)&&(funct==JR) || (funct==JALR))begin
         CtrlPC = 2'd3; // Jumps using Register.
         //$display("Ctrl PC Jump Register");
     end else begin CtrlPC = 2'd0; /*/$display("Ctrl PC No Jump/Branch");*/end // No jumps or branches, just increment to next word
@@ -154,6 +153,7 @@ always @(*) begin
         CtrlALUOp = 5'd5;//OR from ALUOps
     end else if((op==SPECIAL)&&(funct==SLL))begin
         CtrlALUOp = 5'd7;//SLL from ALUOps
+        $display("ALU Op = 7 (SLL)");
     end else if((op==SPECIAL)&&(funct==SLLV))begin
         CtrlALUOp = 5'd8;//SLLV from ALUOps
     end else if((op==SPECIAL)&&(funct==SRA))begin
@@ -161,6 +161,7 @@ always @(*) begin
     end else if((op==SPECIAL)&&(funct==SRAV))begin
         CtrlALUOp = 5'd12;//SRAV from ALUOps
     end else if((op==SPECIAL)&&(funct==SRL))begin
+        $display("ALU Op = 7 (SRL)");
         CtrlALUOp = 5'd9;//SRL from ALUOps
     end else if((op==SPECIAL)&&(funct==SRLV))begin
         CtrlALUOp = 5'd10;//SRLV from ALUOps
@@ -192,7 +193,7 @@ always @(*) begin
     //CtrlALUSrc logic
     if((op==ADDIU) || (op==ANDI) || (op==LUI) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
         CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0]
-    end else if((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRAV) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL))))begin 
+    end else if((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL))))begin 
         CtrlALUSrc = 0;///ALU Bus B is fed from rt.
     end else begin CtrlALUSrc = 1'bx;end
        

rtl/mips_cpu_memory.v

@@ -56,7 +56,7 @@ module mips_cpu_memory(
 
     //Synchronous write path
     always_ff @(posedge clk) begin
-        //$display("Instruction Read: %h", instr_readdata);
+        $display("Instruction Read: %h", instr_readdata);
         //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
         if (!data_read & data_write) begin              //cannot read and write to memory in the same cycle
             if (instr_address != data_address) begin    //cannot modify the instruction being read

rtl/mips_cpu_regfile.v

@@ -22,10 +22,8 @@ end
 
 assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory
 
-always_comb begin
+assign readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector
-	readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector
+assign readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector
-	readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector
-end
 
 always_ff @(negedge clk) begin
 	if (writereg == 5'b00000) begin
@@ -61,6 +59,9 @@ always_ff @(negedge clk) begin
 				endcase // readdata1[1:0]
 			end
 			6'b100010: begin //lwl, load word left
+				$display("LWLWLWLWLWLWWL");
+				$display(readdata1[1:0]);
+				$display("%h",memory[writereg]);
 				case (readdata1[1:0])
 					2'b00: memory[writereg][31:24] <= writedata[7:0];
 					2'b01: memory[writereg][31:16] <= writedata[15:0];

test/test_mips_cpu_custom.sh

@@ -1,6 +1,6 @@
 #!/bin/bash
-
+#:'
-#arithmetic
+# arithmetic
 bash test/test_mips_cpu_harvard.sh rtl addu             #Pass
 bash test/test_mips_cpu_harvard.sh rtl addiu            #Pass
 bash test/test_mips_cpu_harvard.sh rtl ori              #Pass
@@ -10,35 +10,57 @@ bash test/test_mips_cpu_harvard.sh rtl or               #Pass
 bash test/test_mips_cpu_harvard.sh rtl xor              #Pass
 bash test/test_mips_cpu_harvard.sh rtl xori             #Pass
 bash test/test_mips_cpu_harvard.sh rtl subu             #Pass
+#bash test/test_mips_cpu_harvard.sh rtl div
+#bash test/test_mips_cpu_harvard.sh rtl divu
+#bash test/test_mips_cpu_harvard.sh rtl mthi
+#bash test/test_mips_cpu_harvard.sh rtl mtlo
+#bash test/test_mips_cpu_harvard.sh rtl mult
+#bash test/test_mips_cpu_harvard.sh rtl multu
 
 
-#load & store
+# branches
 bash test/test_mips_cpu_harvard.sh rtl beq              #Pass
 bash test/test_mips_cpu_harvard.sh rtl bgez             #Pass
-#bash test/test_mips_cpu_harvard.sh rtl bgezal
+#bash test/test_mips_cpu_harvard.sh rtl bgezal          #Place return address thing how??
 bash test/test_mips_cpu_harvard.sh rtl bgtz             #Pass
 bash test/test_mips_cpu_harvard.sh rtl blez             #Pass
-#bash test/test_mips_cpu_harvard.sh rtl bltz
+#bash test/test_mips_cpu_harvard.sh rtl bltz            #Probably fails due to jump register thing?
 bash test/test_mips_cpu_harvard.sh rtl bltzal           #Pass
 bash test/test_mips_cpu_harvard.sh rtl bne              #Pass
 
+# jumps
+#bash test/test_mips_cpu_harvard.sh rtl j
+#bash test/test_mips_cpu_harvard.sh rtl jalr
+#bash test/test_mips_cpu_harvard.sh rtl jal
+#bash test/test_mips_cpu_harvard.sh rtl jr
 
 # shift
-#bash test/test_mips_cpu_harvard.sh rtl sll
+bash test/test_mips_cpu_harvard.sh rtl sll              #Pass
-#bash test/test_mips_cpu_harvard.sh rtl srl
+bash test/test_mips_cpu_harvard.sh rtl srl              #Pass
 #bash test/test_mips_cpu_harvard.sh rtl sra
 #bash test/test_mips_cpu_harvard.sh rtl srav
 #bash test/test_mips_cpu_harvard.sh rtl srlv
+#'
 
 
-
+# load & store
-# 
+bash test/test_mips_cpu_harvard.sh rtl lw               #Pass
+bash test/test_mips_cpu_harvard.sh rtl lb
+bash test/test_mips_cpu_harvard.sh rtl lbu
+bash test/test_mips_cpu_harvard.sh rtl lh
+bash test/test_mips_cpu_harvard.sh rtl lhu
+bash test/test_mips_cpu_harvard.sh rtl lui
+bash test/test_mips_cpu_harvard.sh rtl lwl
+bash test/test_mips_cpu_harvard.sh rtl lwr
 #bash test/test_mips_cpu_harvard.sh rtl sw
+#bash test/test_mips_cpu_harvard.sh rtl sb
+#bash test/test_mips_cpu_harvard.sh rtl sh
 
 
+# set on less than
 #bash test/test_mips_cpu_harvard.sh rtl slti
 #bash test/test_mips_cpu_harvard.sh rtl sltiu           
 #bash test/test_mips_cpu_harvard.sh rtl slt             # missing
-bash test/test_mips_cpu_harvard.sh rtl sltu             #Pass
+#bash test/test_mips_cpu_harvard.sh rtl sltu             #Pass
 
 

test/test_mips_cpu_harvard.sh

@@ -12,6 +12,7 @@ do
     SRC_TEMP+=${SRC_DIR}/${src}" ";
 done
 SRC=${SRC_TEMP}
+#echo ${SRC};
 
 # Instruction Argument
 INSTR=${2:-"No instruction specified: running all testcases"};  # e.g. addiu
@@ -20,17 +21,18 @@ INSTR=${2:-"No instruction specified: running all testcases"};  # e.g. addiu
 if [[ ${INSTR} == "No instruction specified: running all testcases" ]];
 then
     # All Testcase Files
-    TESTCASES=$(find ./inputs ! -name '*ref*'  ! -name '*log*' ! -name '*out*' ! -name 'inputs' | sed 's#.*/##');
+    TESTCASES=$(find ./inputs ! -name '*ref*'  ! -name '*log*' ! -name '*out*' ! -name 'inputs' ! -name 'data' | sed 's#.*/##');
     #echo ${TESTCASES}
     for TESTCASE in ${TESTCASES}
     do
         # Run Each Testcase File
         TESTCASE="${TESTCASE%%.*}";
         #echo ${TESTCASE};
-#/mnt/c/Windows/System32/cmd.exe /C \
+/mnt/c/Windows/System32/cmd.exe /C \
 iverilog -Wall -g2012 \
     -s mips_cpu_harvard_tb \
-    -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${TESTCASE}.txt\"
+    -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${TESTCASE}.txt\" \
+    -P mips_cpu_harvard_tb.MEM_INIT_FILE=\"inputs/${TESTCASE}.data.txt\" \
     -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \
     ${SRC} 2> /dev/null
 /mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${TESTCASE}.log.txt;       # log file for debugging (contains $display)