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https://github.com/supleed2/ELEC50010-IAC-CW.git
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Updated PC/Harvard, should work with delay slot
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3a2fde81b2
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27
rtl/mips_cpu_cpc.v
Normal file
27
rtl/mips_cpu_cpc.v
Normal file
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@ -0,0 +1,27 @@
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module cpc(
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input logic clk,
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input logic rst,
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input logic[31:0] cpc_in,
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output logic[31:0] cpc_out
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);
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reg[31:0] cpc_curr;
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initial begin
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cpc_curr = 32'hBFC00000;
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end // initial
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always_comb begin
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if (rst) begin
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cpc_curr = 32'hBFC00000;
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end else begin
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cpc_curr = cpc_in;
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end
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end
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always_ff @(posedge clk) begin
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cpc_out <= cpc_curr;
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end
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endmodule // pc
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@ -42,22 +42,6 @@ always_comb begin
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in_readreg2 = instr_readdata[20:16];
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in_opcode = instr_readdata[31:26];
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//Picking what the next value of PC should be.
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case(out_PC)
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2'd0: begin
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in_pc_in = out_pc_out + 32'd4;//No branch or jump or load, so no delay slot.
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end
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2'd1: begin
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in_pc_in = //help
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end
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2'd2: begin
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in_pc_in = //my brain hurts
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end
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2'd3: begin
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in_pc_in = //I need to sleep......
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end
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endcase
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//Picking what register should be written to.
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case(out_RegDst)
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2'd0:begin
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@ -95,11 +79,13 @@ always_comb begin
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endcase
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end
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pc pc(
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mips_cpu_pc pc(
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//PC inputs
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.clk(clk),//clk taken from the Standard signals
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.rst(reset),//clk taken from the Standard signals
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.pc_in(in_pc_in),//what the pc will output on the next clock cycle taken from either: PC itself + 4(Normal/Default Operation); or 16-bit signed valued taken from Instr[15-0] sign extend to 32bit then shifted by 2 then added to PC + 4(Branch Operation); or 26-bit instruction address taken from J-type instr[25-0] shifted left by 2 then concatanated to form Jump Address (PC-region branch); or from the GPR rs.
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.Instr(instr_readdata),//what the pc will output on the next clock cycle taken from either: PC itself + 4(Normal/Default Operation); or 16-bit signed valued taken from Instr[15-0] sign extend to 32bit then shifted by 2 then added to PC + 4(Branch Operation); or 26-bit instruction address taken from J-type instr[25-0] shifted left by 2 then concatanated to form Jump Address (PC-region branch); or from the GPR rs.
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.JumpReg(out_readdata1),
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.pc_ctrl(out_PC),
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//PC outputs
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.pc_out(out_pc_out)//What the pc outputs at every clock edge that goes into the 'Read address' port of Instruction Memory.
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);
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27
rtl/mips_cpu_npc.v
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27
rtl/mips_cpu_npc.v
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@ -0,0 +1,27 @@
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module npc(
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input logic clk,
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input logic rst,
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input logic[31:0] npc_in,
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output logic[31:0] npc_out
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);
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reg[31:0] npc_curr;
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initial begin
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npc_curr = (32'hBFC00000 + 32'd4);
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end // initial
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always_comb begin
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if (rst) begin
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npc_curr = (32'hBFC00000 + 32'd4);
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end else begin
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npc_curr = npc_in;
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end
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end
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always_ff @(posedge clk) begin
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npc_out <= npc_curr;
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end
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endmodule // pc
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@ -1,27 +1,51 @@
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module pc(
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input logic clk,
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input logic rst,
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input logic[31:0] pc_in,
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input logic[31:0] Instr,
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input logic[31:0] JumpReg,
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input logic[1:0] pc_ctrl
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output logic[31:0] pc_out
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);
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reg[31:0] pc_curr;
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logic[31:0] out_cpc_out;
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logic[31:0] out_npc_out;
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logic[31:0] in_npc_in;
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initial begin
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pc_curr = 32'hBFC00000;
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end // initial
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assign pc_out = out_cpc_out;
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always_comb begin
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if (rst) begin
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pc_curr = 32'hBFC00000;
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end else begin
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pc_curr = pc_in;
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case(pc_ctrl)
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2'd0: begin
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in_npc_in = out_npc_out + 32'd4;//No branch or jump or load.
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end
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2'd1: begin
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in_npc_in = out_npc_out + {{14{Instr[15]}}, Instr[15:0], 2'b00};
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end
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2'd2: begin
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in_npc_in = {out_npc_out[31:28], Instr[25:0], 2'b00};
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end
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2'd3: begin
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in_npc_in = JumpReg;
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end
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endcase
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end
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always_ff @(posedge clk) begin
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pc_out <= pc_curr;
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end
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mips_cpu_cpc cpc(
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//Inputs for cpc
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.clk(clk),
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.rst(rst),
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.cpc_in(out_npc_out),
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//Outputs for cpc
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.cpc_out(out_cpc_out)
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);
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endmodule // pc
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mips_cpu_cpc npc(
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//Inputs for npc
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.clk(clk),
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.rst(rst),
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.npc_in(in_npc_in),
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//Outputs for npc
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.npc_out(out_npc_out)
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);
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endmodule
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