Updated PC/Harvard, should work with delay slot

This commit is contained in:
jc4419 2020-12-13 15:37:44 +04:00
parent 3a2fde81b2
commit be27fdc1ce
4 changed files with 97 additions and 33 deletions

27
rtl/mips_cpu_cpc.v Normal file
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@ -0,0 +1,27 @@
module cpc(
input logic clk,
input logic rst,
input logic[31:0] cpc_in,
output logic[31:0] cpc_out
);
reg[31:0] cpc_curr;
initial begin
cpc_curr = 32'hBFC00000;
end // initial
always_comb begin
if (rst) begin
cpc_curr = 32'hBFC00000;
end else begin
cpc_curr = cpc_in;
end
end
always_ff @(posedge clk) begin
cpc_out <= cpc_curr;
end
endmodule // pc

View file

@ -42,22 +42,6 @@ always_comb begin
in_readreg2 = instr_readdata[20:16];
in_opcode = instr_readdata[31:26];
//Picking what the next value of PC should be.
case(out_PC)
2'd0: begin
in_pc_in = out_pc_out + 32'd4;//No branch or jump or load, so no delay slot.
end
2'd1: begin
in_pc_in = //help
end
2'd2: begin
in_pc_in = //my brain hurts
end
2'd3: begin
in_pc_in = //I need to sleep......
end
endcase
//Picking what register should be written to.
case(out_RegDst)
2'd0:begin
@ -95,11 +79,13 @@ always_comb begin
endcase
end
pc pc(
mips_cpu_pc pc(
//PC inputs
.clk(clk),//clk taken from the Standard signals
.rst(reset),//clk taken from the Standard signals
.pc_in(in_pc_in),//what the pc will output on the next clock cycle taken from either: PC itself + 4(Normal/Default Operation); or 16-bit signed valued taken from Instr[15-0] sign extend to 32bit then shifted by 2 then added to PC + 4(Branch Operation); or 26-bit instruction address taken from J-type instr[25-0] shifted left by 2 then concatanated to form Jump Address (PC-region branch); or from the GPR rs.
.Instr(instr_readdata),//what the pc will output on the next clock cycle taken from either: PC itself + 4(Normal/Default Operation); or 16-bit signed valued taken from Instr[15-0] sign extend to 32bit then shifted by 2 then added to PC + 4(Branch Operation); or 26-bit instruction address taken from J-type instr[25-0] shifted left by 2 then concatanated to form Jump Address (PC-region branch); or from the GPR rs.
.JumpReg(out_readdata1),
.pc_ctrl(out_PC),
//PC outputs
.pc_out(out_pc_out)//What the pc outputs at every clock edge that goes into the 'Read address' port of Instruction Memory.
);

27
rtl/mips_cpu_npc.v Normal file
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@ -0,0 +1,27 @@
module npc(
input logic clk,
input logic rst,
input logic[31:0] npc_in,
output logic[31:0] npc_out
);
reg[31:0] npc_curr;
initial begin
npc_curr = (32'hBFC00000 + 32'd4);
end // initial
always_comb begin
if (rst) begin
npc_curr = (32'hBFC00000 + 32'd4);
end else begin
npc_curr = npc_in;
end
end
always_ff @(posedge clk) begin
npc_out <= npc_curr;
end
endmodule // pc

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@ -1,27 +1,51 @@
module pc(
input logic clk,
input logic rst,
input logic[31:0] pc_in,
input logic[31:0] Instr,
input logic[31:0] JumpReg,
input logic[1:0] pc_ctrl
output logic[31:0] pc_out
);
reg[31:0] pc_curr;
logic[31:0] out_cpc_out;
logic[31:0] out_npc_out;
logic[31:0] in_npc_in;
initial begin
pc_curr = 32'hBFC00000;
end // initial
assign pc_out = out_cpc_out;
always_comb begin
if (rst) begin
pc_curr = 32'hBFC00000;
end else begin
pc_curr = pc_in;
case(pc_ctrl)
2'd0: begin
in_npc_in = out_npc_out + 32'd4;//No branch or jump or load.
end
2'd1: begin
in_npc_in = out_npc_out + {{14{Instr[15]}}, Instr[15:0], 2'b00};
end
2'd2: begin
in_npc_in = {out_npc_out[31:28], Instr[25:0], 2'b00};
end
2'd3: begin
in_npc_in = JumpReg;
end
endcase
end
always_ff @(posedge clk) begin
pc_out <= pc_curr;
end
mips_cpu_cpc cpc(
//Inputs for cpc
.clk(clk),
.rst(rst),
.cpc_in(out_npc_out),
//Outputs for cpc
.cpc_out(out_cpc_out)
);
endmodule // pc
mips_cpu_cpc npc(
//Inputs for npc
.clk(clk),
.rst(rst),
.npc_in(in_npc_in),
//Outputs for npc
.npc_out(out_npc_out)
);
endmodule