supleed2/ELEC50010-IAC-CW
1
0
Fork 0
mirror of https://github.com/supleed2/ELEC50010-IAC-CW.git synced 2024-12-22 21:35:48 +00:00
Code Issues Packages Projects Releases Wiki Activity

Added jump type testcase in ref.txt

Browse source
This commit is contained in:
theexecutor13 2020-12-10 00:10:38 +08:00 committed by GitHub
parent 7e6bc7c370
commit b17158489f
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 202 additions and 125 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

327
inputs/reference.txt
View file

@ -1,124 +1,124 @@
== Instruction == == Instruction ==
C code C code
Assembly code Assembly code
Hex code Hex code
Reference Output Reference Output
================ ================
== ADDIU Add immediate unsigned (no overflow) == == ADDIU Add immediate unsigned (no overflow) ==
== ADDU Add unsigned (no overflow) == == ADDU Add unsigned (no overflow) ==
int main(void) { int main(void) {
int a = 3 + 5; int a = 3 + 5;
} }
ORI $4,$0,3 ORI $4,$0,3
ORI $5,$0,5 ORI $5,$0,5
ADDU $2,$4,$5 ADDU $2,$4,$5
JR $0 JR $0
34040003 34040003
34050005 34050005
00851021 00851021
00000008 00000008
register_v0 = 8 register_v0 = 8
== AND Bitwise and == == AND Bitwise and ==
ANDI Bitwise and immediate ANDI Bitwise and immediate
==BEQ Branch on equal== ==BEQ Branch on equal==
ORI $4,$0,5 ORI $4,$0,5
ORI $5,$0,5 ORI $5,$0,5
BEQ $4,$5,2 BEQ $4,$5,2
ADDIU $6,$6,0 ADDIU $6,$6,0
JR $0 JR $0
ORI $2,$0,1 ORI $2,$0,1
JR $0 JR $0
50004043 50004043
50005043 50005043
20005801 20005801
00006C42 00006C42
80000000 80000000
10002043 10002043
80000000 80000000
register_v0 = 1 register_v0 = 1
==BGEZ Branch on greater than or equal to zero== ==BGEZ Branch on greater than or equal to zero==
ORI $4,$0,3 ORI $4,$0,3
BGEZ $4,2 BGEZ $4,2
ADDIU $6,$6,0 ADDIU $6,$6,0
JR $0 JR $0
ORI $2,$0,1 ORI $2,$0,1
JR $0 JR $0
30004043 30004043
20001840 20001840
00006C42 00006C42
80000000 80000000
10002043 10002043
80000000 80000000
register_v0 = 1 register_v0 = 1
==BGEZAL Branch on non-negative (>=0) and link== ==BGEZAL Branch on non-negative (>=0) and link==
ORI $4,$0,3 ORI $4,$0,3
BGEZAL $4,3 BGEZAL $4,3
ADDIU $6,$6,0 ADDIU $6,$6,0
ADDIU $2,$2,1 ADDIU $2,$2,1
JR $0 JR $0
ORI $2,$0,1 ORI $2,$0,1
JR $31 JR $31
30004043 30004043
30001940 30001940
00006C42 00006C42
10002442 10002442
80000000 80000000
10002043 10002043
80000000 80000000
register_v0 = 2 register_v0 = 2
==BGTZ Branch on greater than zero==
==BGTZ Branch on greater than zero==
ORI $4,$0,3 ORI $4,$0,3
BGTZ $4,2 BGTZ $4,2
ADDIU $6,$6,0 ADDIU $6,$6,0
JR $0 JR $0
ORI $2,$0,1 ORI $2,$0,1
JR $0 JR $0
30004043 30004043
200008C1 200008C1
00006C42 00006C42
80000000 80000000
10002043 10002043
80000000 80000000
register_v0 = 1 register_v0 = 1
==BLEZ Branch on less than or equal to zero== ==BLEZ Branch on less than or equal to zero==
ORI $4,$0,-1 ORI $4,$0,-1
BLEZ $4,2 BLEZ $4,2
ADDIU $6,$6,0 ADDIU $6,$6,0
JR $0 JR $0
ORI $2,$0,1 ORI $2,$0,1
JR $0 JR $0
FFFF4043 FFFF4043
20000881 20000881
00006C42 00006C42
@ -126,56 +126,56 @@ FFFF4043
10002043 10002043
80000000 80000000
register_v0 = 1 register_v0 = 1
==BLTZ Branch on less than zero== ==BLTZ Branch on less than zero==
ORI $4,$0,-1 ORI $4,$0,-1
BLTZ $4,2 BLTZ $4,2
ADDIU $6,$6,0 ADDIU $6,$6,0
JR $0 JR $0
ORI $2,$0,1 ORI $2,$0,1
JR $0 JR $0
FFFF4043 FFFF4043
20000840 20000840
00006C42 00006C42
80000000 80000000
10002043 10002043
80000000 80000000
register_v0 = 1 register_v0 = 1
==BLTZAL Branch on less than zero and link== ==BLTZAL Branch on less than zero and link==
ORI $4,$0,-1 ORI $4,$0,-1
BLTZAL $4,3 BLTZAL $4,3
ADDIU $6,$6,0 ADDIU $6,$6,0
ADDIU $2,$2,1 ADDIU $2,$2,1
JR $0 JR $0
ORI $2,$0,1 ORI $2,$0,1
JR $31 JR $31
FFFF4043 FFFF4043
20000940 20000940
00006C42 00006C42
10002442 10002442
80000000 80000000
10002043 10002043
80000000 80000000
register_v0 = 2 register_v0 = 2
==BNE Branch on not equal== ==BNE Branch on not equal==
ORI $4,$0,3 ORI $4,$0,3
ORI $5,$0,5 ORI $5,$0,5
BNE $4,$5,2 BNE $4,$5,2
ADDIU $6, $6, 0 ADDIU $6, $6, 0
JR $0 JR $0
ORI $2,$0,1 ORI $2,$0,1
JR $ JR $
30004043 30004043
50005043 50005043
20005841 20005841
@ -183,42 +183,119 @@ JR $
80000000 80000000
10002043 10002043
80000000 80000000
register_v0 = 1 register_v0 = 1
DIV Divide DIV Divide
DIVU Divide unsigned DIVU Divide unsigned
J Jump
JALR Jump and link register ==J Jump==
JAL Jump and link J 4
JR Jump register NOP
LB Load byte JR $0
LBU Load byte unsigned NOP
LH Load half-word ORI $2,$0,1
LHU Load half-word unsigned JR $0
LUI Load upper immediate
LW Load word 08000004
LWL Load word left 00000000
LWR Load word right 00000008
MTHI Move to HI 00000000
MTLO Move to LO 34020001
MULT Multiply 00000008
MULTU Multiply unsigned
OR Bitwise or register_v0 = 1
ORI Bitwise or immediate
SB Store byte ==JALR Jump and link register==
SH Store half-word ORI $5,$0,1C
SLL Shift left logical LUI $5,BFC0
SLLV Shift left logical variable JALR $4,$5
SLT Set on less than (signed) NOP
SLTI Set on less than immediate (signed) ADDIU $2,$2,1
SLTIU Set on less than immediate unsigned JR $0
SLTU Set on less than unsigned NOP
SRA Shift right arithmetic ORI $2,$0,1
SRAV Shift right arithmetic JR $4
SRL Shift right logical
SRLV Shift right logical variable 3405001C
SUBU Subtract unsigned 3C05BCF0
SW Store word 00A02009
XOR Bitwise exclusive or 00000000
XORI Bitwise exclusive or immediate 24420001
00000008
00000000
34020001
00800008
24C60000
register_v0 = 2
==JAL Jump and link==
JAL 5
NOP
ADDIU $2,$2,1
JR $0
NOP
ORI $2,$0,1
JR $31
0C000005
00000000
24420001
00000008
00000000
34020001
03E00008
register_v0 = 2
==JR Jump register==
ORI $5,$0,14
LUI $5,BFC0
JR $5
NOP
JR $0
NOP
ORI $2,$0,1
JR $0
34050014
3C05BCF0
00A00008
00000000
00000008
34020001
00000008
register_v0 = 1
LB Load byte
LBU Load byte unsigned
LH Load half-word
LHU Load half-word unsigned
LUI Load upper immediate
LW Load word
LWL Load word left
LWR Load word right
MTHI Move to HI
MTLO Move to LO
MULT Multiply
MULTU Multiply unsigned
OR Bitwise or
ORI Bitwise or immediate
SB Store byte
SH Store half-word
SLL Shift left logical
SLLV Shift left logical variable
SLT Set on less than (signed)
SLTI Set on less than immediate (signed)
SLTIU Set on less than immediate unsigned
SLTU Set on less than unsigned
SRA Shift right arithmetic
SRAV Shift right arithmetic
SRL Shift right logical
SRLV Shift right logical variable
SUBU Subtract unsigned
SW Store word
XOR Bitwise exclusive or
XORI Bitwise exclusive or immediate