supleed2/ELEC50010-IAC-CW
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Completed wrapper, to be tested

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This commit is contained in:
Aadi Desai 2020-12-11 19:45:00 +00:00
parent 714b74ec83
commit af7645b5b0
1 changed files with 56 additions and 16 deletions
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58
rtl/mips_cpu_bus.v
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@ -22,6 +22,10 @@ logic clk_internal; // modulated clock to be passed to harvard cpu
logic[31:0] harvard_instr_address; // instr addr from pc
logic harvard_read; // harvard cpu read flag
logic harvard_write; // harvard cpu write flag
logic[31:0] harvard_data_address; // data addr from ALU
logic[31:0] harvard_readdata; // <= data read from Avalon MM Device
logic[3:0] write_byteenable; // byteenable calculator for partial write
logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly
initial begin
clk_internal = 1'b0;
@ -33,29 +37,33 @@ initial begin
read = 1'b0;
writedata = 32'h00000000;
byteenable = 4'b0000;
clk_state = 0;
end
always_ff @(posedge clk) begin // CLK Rising Edge
if (waitrequest) begin
end else begin
if (!waitrequest && !clk_state) begin
case (n_state)
2'b00: begin // fetch
clk_internal <= 1'b1;
state <= 2'b00;
end
2'b01: begin // execute
state <= 2'b10;
state <= 2'b01;
instr_reg <= readdata;
end
2'b10: begin // read
state <= 2'b10;
end
2'b11: begin // write
state <= 2'b11;
end
endcase // state
end
clk_state <= 1'b1;
end
always_ff @(negedge clk) begin // CLK Falling Edge
if (!waitrequest && clk_state) begin
case (state)
2'b00: // nothing happens on fetch negedge
2'b01: begin // execute negedge
@ -63,7 +71,15 @@ always_ff @(negedge clk) begin // CLK Falling Edge
clk_internal <= 1'b0;
end // otherwise do nothing
end
2'b10: begin
clk_internal <= 1'b0;
end
2'b11: begin
clk_internal <= 1'b0;
end
endcase
end
clk_state <= 1'b0;
end
always_comb begin
@ -79,24 +95,48 @@ always_comb begin
byteenable = 4'b0000;
end else begin
case (state)
2'b00: begin
2'b00: begin // connecting wires when in fetch state
address = harvard_instr_address;
read = 1'b1;
write = 1'b0;
byteenable = 4'b1111;
harvard_readdata = 32'h00000000;
writedata = 32'h00000000;
n_state = 2'b01;
end
2'b01: begin
2'b01: begin // connecting wires when in execute state
address = 32'h00000000;
read = 1'b0;
write = 1'b0;
byteenable = 4'b0000;
harvard_readdata = 32'h00000000;
writedata = 32'h00000000;
if (harvard_read) begin
n_state = 2'b10; // next state is read
end else if (harvard_write) begin
n_state = 2'b11; // next state is write
end else begin
n_state 2'b00; // next state is fetch
n_state = 2'b00; // next state is fetch
end
end
2'b10: begin // connecting wires when in read state
address = harvard_data_address;
read = 1'b1;
write = 1'b0;
byteenable = 4'b1111;
harvard_readdata = readdata;
writedata = 32'h00000000;
n_state = 2'b00;
end
2'b11: begin // connecting wires when in write state
address = harvard_data_address;
read = 1'b0;
write = 1'b1;
byteenable = write_byteenable;
harvard_readdata = 32'h00000000;
writedata = harvard_writedata;
n_state = 2'b00;
end
endcase // state
end
end
@ -109,11 +149,11 @@ mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper
.clk_enable(1'b0), // unused clock enable, input
.instr_address(harvard_instr_address), // instr addr from pc, output
.instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input
.data_address(######), // output
.data_address(harvard_data_address), // harvard data memory address, output
.data_write(harvard_write), // harvard write flag, output
.data_read(harvard_read), // harvard read flag, output
.data_writedata(######), // output
.data_readdata(######) // input
.data_writedata(harvard_writedata), // data output from regfile readport2, output
.data_readdata(harvard_readdata) // data in from read instruction, input
);
endmodule : mips_cpu_bus