From af29f22651213a870a8cafea6fcd4bf58f3eb831 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 13:54:26 +0000 Subject: [PATCH] Merge branch 'main' into bus_wrapper Changes to be duplicated for bus version --- inputs/addiu/addiu-1.txt | 2 +- inputs/addiu/addiu-2.ref.txt | 1 - inputs/addiu/addiu-2.txt | 2 - inputs/addu/addu-1.txt | 2 +- inputs/and/and-1.txt | 2 +- inputs/andi/andi-1.txt | 2 +- inputs/beq/beq-2.ref.txt | 1 - inputs/beq/beq-2.txt | 8 - inputs/bgez/bgez-2.ref.txt | 1 - inputs/bgez/bgez-2.txt | 7 - inputs/lb/lb-1.txt | 2 +- inputs/lbu/lbu-1.txt | 2 +- inputs/lh/lh-1.txt | 2 +- inputs/lhu/lhu-1.txt | 2 +- inputs/lw/lw-1.txt | 2 +- inputs/lwl/lwl-1.txt | 2 +- inputs/lwr/lwr-1.txt | 2 +- inputs/or/or-1.txt | 2 +- inputs/ori/ori-1.ref.txt | 2 +- inputs/ori/ori-1.txt | 6 +- inputs/ori/ori-2.ref.txt | 1 - inputs/ori/ori-2.txt | 4 - inputs/sll/sll-1.txt | 2 +- inputs/sllv/sllv-1.txt | 2 +- inputs/slt/slt-1.txt | 4 +- inputs/slt/slt-2.ref.txt | 1 - inputs/slt/slt-2.txt | 4 - inputs/sra/sra-1.txt | 3 +- inputs/srav/srav-1.txt | 3 +- inputs/srl/srl-1.txt | 2 +- inputs/srlv/srlv-1.txt | 2 +- inputs/subu/subu-1.txt | 2 +- inputs/xori/xori-1.txt | 4 +- reference.txt | 869 ------------------ .../Instructions.xlsx | Bin mips-isa.pdf => reference/mips-isa.pdf | Bin reference/reference.txt | 604 ++++++++---- structure.png => reference/structure.png | Bin test/test_mips_cpu_harvard.sh | 4 +- {rtl => testbench}/mips_cpu_memory.v | 0 40 files changed, 480 insertions(+), 1083 deletions(-) delete mode 100644 inputs/addiu/addiu-2.ref.txt delete mode 100644 inputs/addiu/addiu-2.txt delete mode 100644 inputs/beq/beq-2.ref.txt delete mode 100644 inputs/beq/beq-2.txt delete mode 100644 inputs/bgez/bgez-2.ref.txt delete mode 100644 inputs/bgez/bgez-2.txt delete mode 100644 inputs/ori/ori-2.ref.txt delete mode 100644 inputs/ori/ori-2.txt delete mode 100644 inputs/slt/slt-2.ref.txt delete mode 100644 inputs/slt/slt-2.txt delete mode 100644 reference.txt rename Instructions.xlsx => reference/Instructions.xlsx (100%) rename mips-isa.pdf => reference/mips-isa.pdf (100%) rename structure.png => reference/structure.png (100%) rename {rtl => testbench}/mips_cpu_memory.v (100%) diff --git a/inputs/addiu/addiu-1.txt b/inputs/addiu/addiu-1.txt index 62290ae..7401d7b 100644 --- a/inputs/addiu/addiu-1.txt +++ b/inputs/addiu/addiu-1.txt @@ -1,3 +1,3 @@ 3404000a +00000008 24820014 -00000008 \ No newline at end of file diff --git a/inputs/addiu/addiu-2.ref.txt b/inputs/addiu/addiu-2.ref.txt deleted file mode 100644 index 9a03714..0000000 --- a/inputs/addiu/addiu-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -10 \ No newline at end of file diff --git a/inputs/addiu/addiu-2.txt b/inputs/addiu/addiu-2.txt deleted file mode 100644 index 664859c..0000000 --- a/inputs/addiu/addiu-2.txt +++ /dev/null @@ -1,2 +0,0 @@ -2442000A -00000008 \ No newline at end of file diff --git a/inputs/addu/addu-1.txt b/inputs/addu/addu-1.txt index 1c079df..5d98337 100644 --- a/inputs/addu/addu-1.txt +++ b/inputs/addu/addu-1.txt @@ -1,4 +1,4 @@ 34040003 34050005 +00000008 00851021 -00000008 \ No newline at end of file diff --git a/inputs/and/and-1.txt b/inputs/and/and-1.txt index 7a287c6..f50bee1 100644 --- a/inputs/and/and-1.txt +++ b/inputs/and/and-1.txt @@ -2,5 +2,5 @@ 34A5cccc 3c04aaaa 3484aaaa +00000008 00851024 -00000008 \ No newline at end of file diff --git a/inputs/andi/andi-1.txt b/inputs/andi/andi-1.txt index ccc9aa9..a927a1b 100644 --- a/inputs/andi/andi-1.txt +++ b/inputs/andi/andi-1.txt @@ -1,4 +1,4 @@ 3c04aaaa 3404aaaa +00000008 3082cccc -00000008 \ No newline at end of file diff --git a/inputs/beq/beq-2.ref.txt b/inputs/beq/beq-2.ref.txt deleted file mode 100644 index 60d3b2f..0000000 --- a/inputs/beq/beq-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -15 diff --git a/inputs/beq/beq-2.txt b/inputs/beq/beq-2.txt deleted file mode 100644 index 07e24de..0000000 --- a/inputs/beq/beq-2.txt +++ /dev/null @@ -1,8 +0,0 @@ -34040005 -34050005 -10850003 -34020005 -00000008 -00000000 -2442000A -00000008 \ No newline at end of file diff --git a/inputs/bgez/bgez-2.ref.txt b/inputs/bgez/bgez-2.ref.txt deleted file mode 100644 index 7813681..0000000 --- a/inputs/bgez/bgez-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -5 \ No newline at end of file diff --git a/inputs/bgez/bgez-2.txt b/inputs/bgez/bgez-2.txt deleted file mode 100644 index 13d6d41..0000000 --- a/inputs/bgez/bgez-2.txt +++ /dev/null @@ -1,7 +0,0 @@ -34040003 -04810003 -00000000 -24420001 -00000000 -24420005 -00000008 \ No newline at end of file diff --git a/inputs/lb/lb-1.txt b/inputs/lb/lb-1.txt index 43aa99a..940d1c7 100644 --- a/inputs/lb/lb-1.txt +++ b/inputs/lb/lb-1.txt @@ -1,3 +1,3 @@ 34041001 +00000008 80820005 -00000008 \ No newline at end of file diff --git a/inputs/lbu/lbu-1.txt b/inputs/lbu/lbu-1.txt index 14f9e84..0c0c283 100644 --- a/inputs/lbu/lbu-1.txt +++ b/inputs/lbu/lbu-1.txt @@ -1,3 +1,3 @@ 34041002 +00000008 90820004 -00000008 \ No newline at end of file diff --git a/inputs/lh/lh-1.txt b/inputs/lh/lh-1.txt index aa12925..f3c6ebd 100644 --- a/inputs/lh/lh-1.txt +++ b/inputs/lh/lh-1.txt @@ -1,3 +1,3 @@ 34041000 +00000008 84820004 -00000008 \ No newline at end of file diff --git a/inputs/lhu/lhu-1.txt b/inputs/lhu/lhu-1.txt index d8bc6f1..f185691 100644 --- a/inputs/lhu/lhu-1.txt +++ b/inputs/lhu/lhu-1.txt @@ -1,3 +1,3 @@ 34041000 +00000008 94820004 -00000008 \ No newline at end of file diff --git a/inputs/lw/lw-1.txt b/inputs/lw/lw-1.txt index 7c6a2ee..702ed31 100644 --- a/inputs/lw/lw-1.txt +++ b/inputs/lw/lw-1.txt @@ -1,3 +1,3 @@ 34041002 +00000008 8C820002 -00000008 \ No newline at end of file diff --git a/inputs/lwl/lwl-1.txt b/inputs/lwl/lwl-1.txt index c682e96..5ba291d 100644 --- a/inputs/lwl/lwl-1.txt +++ b/inputs/lwl/lwl-1.txt @@ -1,4 +1,4 @@ 34041001 34025678 +00000008 88820003 -00000008 \ No newline at end of file diff --git a/inputs/lwr/lwr-1.txt b/inputs/lwr/lwr-1.txt index 633db20..7f2641f 100644 --- a/inputs/lwr/lwr-1.txt +++ b/inputs/lwr/lwr-1.txt @@ -1,4 +1,4 @@ 3C021234 34041002 +00000008 98820003 -00000008 \ No newline at end of file diff --git a/inputs/or/or-1.txt b/inputs/or/or-1.txt index 25df299..7d9b029 100644 --- a/inputs/or/or-1.txt +++ b/inputs/or/or-1.txt @@ -1,4 +1,4 @@ 34040005 34050003 +00000008 00851025 -00000008 \ No newline at end of file diff --git a/inputs/ori/ori-1.ref.txt b/inputs/ori/ori-1.ref.txt index c793025..35ff949 100644 --- a/inputs/ori/ori-1.ref.txt +++ b/inputs/ori/ori-1.ref.txt @@ -1 +1 @@ -7 \ No newline at end of file +65535 \ No newline at end of file diff --git a/inputs/ori/ori-1.txt b/inputs/ori/ori-1.txt index b41478b..35a84da 100644 --- a/inputs/ori/ori-1.txt +++ b/inputs/ori/ori-1.txt @@ -1,3 +1,5 @@ -34020003 -34420005 +3404FFFF +34051234 00000008 +00851025 + diff --git a/inputs/ori/ori-2.ref.txt b/inputs/ori/ori-2.ref.txt deleted file mode 100644 index 35ff949..0000000 --- a/inputs/ori/ori-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -65535 \ No newline at end of file diff --git a/inputs/ori/ori-2.txt b/inputs/ori/ori-2.txt deleted file mode 100644 index b13206a..0000000 --- a/inputs/ori/ori-2.txt +++ /dev/null @@ -1,4 +0,0 @@ -3404FFFF -34052134 -00851025 -00000008 diff --git a/inputs/sll/sll-1.txt b/inputs/sll/sll-1.txt index e03a5d2..8956883 100644 --- a/inputs/sll/sll-1.txt +++ b/inputs/sll/sll-1.txt @@ -1,3 +1,3 @@ 34040003 +00000008 00041080 -00000008 \ No newline at end of file diff --git a/inputs/sllv/sllv-1.txt b/inputs/sllv/sllv-1.txt index d733281..5eaf2c8 100644 --- a/inputs/sllv/sllv-1.txt +++ b/inputs/sllv/sllv-1.txt @@ -1,4 +1,4 @@ 34040002 34050003 +00000008 00851004 -00000008 \ No newline at end of file diff --git a/inputs/slt/slt-1.txt b/inputs/slt/slt-1.txt index 2d14014..d58bdf7 100644 --- a/inputs/slt/slt-1.txt +++ b/inputs/slt/slt-1.txt @@ -1,4 +1,4 @@ -3404000F +3404FFFF 3405000B 00000008 -0085102A \ No newline at end of file +0085102A diff --git a/inputs/slt/slt-2.ref.txt b/inputs/slt/slt-2.ref.txt deleted file mode 100644 index c227083..0000000 --- a/inputs/slt/slt-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -0 \ No newline at end of file diff --git a/inputs/slt/slt-2.txt b/inputs/slt/slt-2.txt deleted file mode 100644 index 013d035..0000000 --- a/inputs/slt/slt-2.txt +++ /dev/null @@ -1,4 +0,0 @@ -3404FFFF -3405000B -0085102A -00000008 \ No newline at end of file diff --git a/inputs/sra/sra-1.txt b/inputs/sra/sra-1.txt index 1cb5924..d7817c1 100644 --- a/inputs/sra/sra-1.txt +++ b/inputs/sra/sra-1.txt @@ -1,3 +1,4 @@ 3C05F000 -00051083 00000008 +00051083 + diff --git a/inputs/srav/srav-1.txt b/inputs/srav/srav-1.txt index 8d6dad2..681d41b 100644 --- a/inputs/srav/srav-1.txt +++ b/inputs/srav/srav-1.txt @@ -1,4 +1,5 @@ 34040002 3C05F000 -00851007 00000008 +00851007 + diff --git a/inputs/srl/srl-1.txt b/inputs/srl/srl-1.txt index 581aa82..4ac3949 100644 --- a/inputs/srl/srl-1.txt +++ b/inputs/srl/srl-1.txt @@ -1,3 +1,3 @@ 34040010 +00000008 00041082 -00000008 \ No newline at end of file diff --git a/inputs/srlv/srlv-1.txt b/inputs/srlv/srlv-1.txt index ae99941..ebd01e3 100644 --- a/inputs/srlv/srlv-1.txt +++ b/inputs/srlv/srlv-1.txt @@ -1,4 +1,4 @@ 34040002 34050010 +00000008 00851006 -00000008 \ No newline at end of file diff --git a/inputs/subu/subu-1.txt b/inputs/subu/subu-1.txt index 7c8a7eb..d4590d9 100644 --- a/inputs/subu/subu-1.txt +++ b/inputs/subu/subu-1.txt @@ -1,4 +1,4 @@ 34040005 34050003 +00000008 00851023 -00000008 \ No newline at end of file diff --git a/inputs/xori/xori-1.txt b/inputs/xori/xori-1.txt index 4fe9205..c85639a 100644 --- a/inputs/xori/xori-1.txt +++ b/inputs/xori/xori-1.txt @@ -1,5 +1,3 @@ 34040005 -3882000F 00000008 -00000000 -00000000 \ No newline at end of file +3882000F diff --git a/reference.txt b/reference.txt deleted file mode 100644 index 493a0f9..0000000 --- a/reference.txt +++ /dev/null @@ -1,869 +0,0 @@ -== Instruction == -Assembly code -Hex code -Reference Output -================ - -==ADDIU Add immediate unsigned (no overflow)== - -ORI $4,$0,0xA -ADDIU $2,$4,20 -JR $0 - -3404000a -24820014 -00000008 - -register_v0 = 30 - -== ADDU Add unsigned (no overflow) == - -ORI $4,$0,3 -ORI $5,$0,5 -ADDU $2,$4,$5 -JR $0 - -34040003 -34050005 -00851021 -00000008 - -register_v0 = 8 - -==AND Bitwise and== - -LUI $5,0xCCCC -ORI $5,$5,0xCCCC -LUI $4,0xAAAA -ORI $4,$4,0xAAAA -AND $2,$4,$5 -JR $0 - -3c05cccc -34A5cccc -3c04aaaa -3484aaaa -00851024 -00000008 - -register_v0 = 0x88888888 - -==ANDI Bitwise and immediate== - -LUI $4,0xAAAA -ORI $4,$0,0xAAAA -ANDI $2,$4,0xCCCC -JR $0 - -3c04aaaa -3404aaaa -3082cccc -00000008 - -register_v0 = 0x00008888 - -==BEQ Branch on equal== - -ORI $4,$0,5 -ORI $5,$0,5 -BEQ $4,$5,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -34040005 -34050005 -10850003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==BGEZ Branch on greater than or equal to zero== - -ORI $4,$0,3 -BGEZ $4,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -34040003 -04810003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -ORI $4,$0,3 -BGEZ $4,3 -NOP -ADDIU $2,$2,1 -NOP -ADDIU $2,$2,5 -JR $0 - -34040003 -04810003 -00000000 -24420001 -00000000 -24420005 -00000008 - -==BGEZAL Branch on non-negative (>=0) and link== - -ORI $4,$0,3 -BGEZAL $4,4 -NOP -ADDIU $2,$2,1 -JR $0 -NOP -ORI $2,$0,1 -JR $31 - -34040003 -04910004 -00000000 -24420001 -00000008 -00000000 -34020001 -03E00008 - -register_v0 = 2 - -==BGTZ Branch on greater than zero== - -ORI $4,$0,3 -BGTZ $4,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -34040003 -1C800003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==BLEZ Branch on less than or equal to zero== - -LUI $4,0xFFFF -BLEZ $4,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -3C05FFFF -18800003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==BLTZ Branch on less than zero== - -LUI $4,0xFFFF -BLTZ $4,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -3C04FFFF -04800003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==BLTZAL Branch on less than zero and link== - -LUI $4,0xFFFF -BLTZAL $4,4 -NOP -ADDIU $2,$2,1 -JR $0 -NOP -ORI $2,$0,1 -JR $31 - -3C05FFFF -04900004 -00000000 -24420001 -00000008 -00000000 -34020001 -03E00008 - -register_v0 = 2 - -==BNE Branch on not equal== - -ORI $4,$0,3 -ORI $5,$0,5 -BNE $4,$5,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -34040003 -34040005 -14850003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==DIV Divide== //May need other testcases for -ve/+ve, -ve/-ve - -ORI $4,$0,3 -ORI $5,$0,9 -DIV $5,$4 -MFHI $4 -MFLO $5 -ADDU $2,$4,$5 -JR $0 - -34040003 -34050009 -00A4001A -00002010 -00002812 -00851021 -00000008 - -register_v0 = 3 - -==DIVU Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve - -LUI $4,0x8000 -ORI $5,$0,2 -DIVU $4,$5 -MFHI $4 -MFLO $5 -ADDU $2,$4,$5 -JR $0 - -3C048000 -34050002 -0085001B -00002010 -00002812 -00851021 -00000008 - -register_v0 = 0x40000000 - -==J Jump== - -J 4 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -08000004 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==JALR Jump and link register== - -LUI $5,0xBFC0 -ORI $5,$0,0x001C -JALR $4,$5 -NOP -ADDIU $2,$2,1 -JR $0 -NOP -ORI $2,$0,1 -JR $4 - -3C05BCF0 -3405001C -00A02009 -00000000 -24420001 -00000008 -00000000 -34020001 -00800008 - -register_v0 = 2 - -==JAL Jump and link== - -JAL 5 -NOP -ADDIU $2,$2,1 -JR $0 -NOP -ORI $2,$0,1 -JR $31 - -0C000005 -00000000 -24420001 -00000008 -00000000 -34020001 -03E00008 - -register_v0 = 2 - -==JR Jump register== - -LUI $5,0xBFC0 -ORI $5,$5,0x0014 -JR $5 -NOP -JR $0 -NOP -ORI $2,$0,0xA -JR $0 - -3C05BFC0 -34A50014 -00A00008 -00000000 -00000008 -3402000A -00000008 - -register_v0 = 10 - -==LB Load byte== - -ORI $4,$0,0x1003 -LB $2,3($4) -JR $0 - --Instruction Hex - -34041000 -80820006 -00000008 - --Memory Hex - -00000000 -008A0000 -00000000 -00000000 - -register_v0 = 0xFFFFFF8A - -==LBU Load byte unsigned== - -ORI $4,$0,0x1003 -LBU $2,3($4) -JR $0 - --Instruction Hex - -34041003 -90820003 -00000008 - --Memory Hex - -00000000 -008A0000 -00000000 -00000000 - -register_v0 = 0x0000008A - -==LH Load half-word== - -ORI $4,$0,0x1003 -LH $2,4($4) -JR $0 - --Instruction Hex - -34041003 -84820004 -00000008 - --Memory Hex - -00000000 -00008123 -00000000 -00000000 - -register_v0 = 0xFFFF8123 - -==LHU Load half-word unsigned== - -ORI $4,$0,0x1003 -LHU $2,4($4) -JR $0 - --Instruction Hex - -34041003 -94820004 -00000008 - --Memory Hex - -00000000 -00008123 -00000000 -00000000 - -register_v0 = 0x00008123 - -==LUI Load upper immediate== - -LUI $2,0x1234 -ORI $2,$2,0x5678 -JR $0 - -3C021234 -34425678 -00000008 - -register_v0 = 0x12345678 - -==LW Load word== - -ORI $4,$0,0x1002 -LW $2, 2($4) -JR $0 - --Instruction Hex - -34041002 -8C820002 -00000008 - --Memory Hex - -00000000 -12345678 -00000000 -00000000 - -register_v0 = 0x12345678 - -==LWL Load word left== - -ORI $4,$0,0x1001 -ORI $2,$0,0x5678 -LWL $2,3($4) -JR $0 - --Instruction Hex - -34041001 -34025678 -88820003 -00000008 - --Memory Hex - -00000000 -AAAA1234 -00000000 -00000000 - -register_v0 = 0x12345678 - -==LWR Load word right== - -LUI $2,0x1234 -ORI $4,$0,0x1002 -LWR $2,3($4) -JR $0 - --Instruction Hex - -3C021234 -34041002 -98820003 -00000008 - --Memory Hex - -00000000 -5678AAAA -00000000 -00000000 - -register_v0 = 0x12345678 - -==MTHI Move to HI== - -ori $4, $0, 5 -mthi $4 -mfhi $2 -jr $0 - -34040005 -00800011 -00001010 -00000008 - -register_v0 = 5 - -==MTLO Move to LO== - -ori $4, $0, 5 -mtlo $4 -mflo $2 -jr $0 - -34040005 -00800013 -00001012 -00000008 - -register_v0 = 5 - -==MULT Multiply== - -ori $4, $0, 4 -ori $5, $0, 3 -mult $4, $5 -mflo $2 -jr $0 - -34040004 -34050003 -00850018 -00001012 -00000008 - -register_v0 = 12 - -==MULTU Multiply unsigned== - -ori $4, $0, 4 -ori $5, $0, 3 -multu $4, $5 -mflo $2 -jr $0 - -34040004 -34050003 -00850019 -00001012 -00000008 - -register_v0 = 12 - -==OR Bitwise or== - -ori $4, $0, 5 -ori $5, $0, 3 -or $2, $4, $5 -jr $0 - -34040005 -34050003 -00851025 -00000008 - -register_v0 = 7 - - -==ORI Bitwise or immediate== - -ori $2, $0, 3 -ori $2, $2, 5 -jr $0 - -34020003 -00000008 -34420005 - -register_v0 = 7 - -ori $4, $0, 0xFFFF -ori $5, $0, 0x1234 -or $2, $4, $5 -jr $0 - -register_v0 = 65535 - -==SB Store byte== - -lui $4, 0x1234 -ori $4, $0, 0x5678 -lui $5, 0xBFC0 -ori $5, $0, 0x001C -sb $4, 0($5) -lb $2, 0($5) -jr $0 - -3C041234 -34045678 -3C05BFC0 -3405001C -A0A40000 -80A20000 -00000008 - -register_v0 = 0x00000078 - -==SH Store half-word== - -lui $4, 0x1234 -ori $4, $0, 0x5678 -lui $5, 0xBFC0 -ori $5, $0, 0x001C -sh $4, 0($5) -lh $2, 0($5) -jr $0 - -3C041234 -34045678 -3C05BFC0 -3405001C -A4A40000 -84A40000 -00000008 - -register_v0 = 0x00005678 - -==SLL Shift left logical== - -ori $4,$0,3 -sll $2,$4,2 -jr $0 - -34040003 -00041080 -00000008 - -register_v0 = 12 - -==SLLV Shift left logical variable== - -ori $4,$0,2 -ori $5,$0,3 -sllv $2,$5,$4 -jr $0 - -34040002 -34050003 -00851004 -00000008 - -register_v0 = 12 - -==SLT Set on less than (signed)== - -ORI $4 $zero 0xFFFF -ORI $5 $zero 0x000B -SLT $2 $4 $5 -jr $0 - -3404FFFF -3405000B -0085102A -00000008 - -register_v0 = 0 - -==SLTI Set on less than immediate (signed)== - -ori $4, $0, 10 -slti $2, $4, 9 -jr $0 - -3404000a -28820009 -00000008 - -register_v0 = 0 - -==SLTIU Set on less than immediate unsigned== - -ori $4, $0, 10 -sltiu $2, $4, 9 -jr $0 - -3404000a -2c820009 -00000008 - -register_v0 = 0 - -==SLTU Set on less than unsigned== - -ori $4, $0, 10 -ori $5, $0, 9 -sltu $2, $4, $5 -jr $0 - -3404000a -34050009 -0085102b -00000008 - -register_v0 = 0 - -==SRA Shift right arithmetic== - -lui $5 $0,0xF000 -srav $2,$5,2 -jr $0 - -3C05F000 -00051083 -00000008 - -register_v0 = 0xFC000000 - -==SRAV Shift right arithmetic variable== - -ori $4,$0,2 -lui $5, 0xF000 -srav $2,$5,$4 -jr $0 - -F000000 -> FC000000 - -34040004 -3C05F000 -00851007 -00000008 - -register_v0 = 0xFC000000 - -==SRL Shift right logical== - -ori $4,$0,16 -srl $2,$4,2 -jr $0 - -34040010 -00041082 -00000008 - -register_v0 = 4 - -==SRLV Shift right logical variable== - -ori $4,$0,2 -ori $5,$0,16 -srlv $2,$5,$4 -jr $0 - -34040002 -34050010 -00851006 -00000008 - -register_v0 = 4 - -==SUBU Subtract unsigned== - -ori $4,$0,5 -ori $5,$0,3 -subu $2,$4,$5 -jr $0 - -34040005 -34050003 -00851023 -00000008 - -register_v0 = 2 - -==SW Store word== - -ori $4, $0, 0xFFFF -ori $5, $0, 0x1008 -sw $4, 4($5) -lw $2, 4($5) -jr $0 - -3404FFFF -34051008 -ACA40004 -8CA20004 -00000008 - -register_v0 = 0x0000FFFF - -ori $4, $0, 0xFFFF -ori $5, $0, 0x1008 -sw $4, -4($5) -lw $2, -4($5) -jr $0 - -3404FFFF -34051008 -ACA4FFFC -8CA2FFFC -00000008 - -register_v0 = 0x0000FFFF - -==XOR Bitwise exclusive or== - -ori $4, $0, 5 -ori $5, $0, 2 -xor $2, $4, $5 -jr $0 - -34040005 -34050002 -00851026 -00000008 - -register_v0 = 7 - -==XORI Bitwise exclusive or immediate== - -ori $4,$0,5 -xori $2,$4,0x000F -jr $0 - -34040005 -3882000F -00000008 - -register_v0 = 10 diff --git a/Instructions.xlsx b/reference/Instructions.xlsx similarity index 100% rename from Instructions.xlsx rename to reference/Instructions.xlsx diff --git a/mips-isa.pdf b/reference/mips-isa.pdf similarity index 100% rename from mips-isa.pdf rename to reference/mips-isa.pdf diff --git a/reference/reference.txt b/reference/reference.txt index 8583183..21d1887 100644 --- a/reference/reference.txt +++ b/reference/reference.txt @@ -1,61 +1,66 @@ == Instruction == -C code Assembly code Hex code Reference Output ================ -ADDIU Add immediate unsigned (no overflow) +==ADDIU Add immediate unsigned (no overflow)== + +ORI $4,$0,0xA +JR $0 +ADDIU $2,$4,20 + +3404000a +00000008 +24820014 + +register_v0 = 30 == ADDU Add unsigned (no overflow) == -int main(void) { - int a = 3 + 5; -} - ORI $4,$0,3 ORI $5,$0,5 -ADDU $2,$4,$5 JR $0 +ADDU $2,$4,$5 34040003 34050005 -00851021 00000008 +00851021 register_v0 = 8 ==AND Bitwise and== -ORI $5,$0,0xCCCC -LUI $5,0xCCCC -ORI $4,$0,0xAAAA -LUI $4,0xAAAA -AND $2,$4,$5 +LUI $5,0xCCCC +ORI $5,$5,0xCCCC +LUI $4,0xAAAA +ORI $4,$4,0xAAAA JR $0 +AND $2,$4,$5 -3405cccc -3c05cccc -3404aaaa +3c05cccc +34A5cccc 3c04aaaa -00851024 +3484aaaa 00000008 +00851024 -register_v0 = 0x88888888 +register_v0 = 0x88888888 / 2290649224 ==ANDI Bitwise and immediate== +LUI $4,0xAAAA ORI $4,$0,0xAAAA -LUI $4,0xAAAA -ANDI $2,$4,0xCCCC JR $0 +ANDI $2,$4,0xCCCC -3404aaaa 3c04aaaa -3082cccc +3404aaaa 00000008 +3082cccc -register_v0 = 0x00008888 +register_v0 = 0x00008888 / 34952 ==BEQ Branch on equal== @@ -171,7 +176,7 @@ NOP ORI $2,$0,1 JR $0 -3C05FFFF +3C04FFFF 04800003 00000000 00000008 @@ -247,15 +252,15 @@ register_v0 = 3 ==DIVU Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve -LUI $4,0x8000 +LUI $4,0x8000 ORI $5,$0,2 DIVU $4,$5 MFHI $4 -MFLO $5 +MFLO $5 ADDU $2,$4,$5 JR $0 -34048000 +3C048000 34050002 0085001B 00002010 @@ -263,7 +268,7 @@ JR $0 00851021 00000008 -register_v0 = 0x40000000 +register_v0 = 0x40000000 / 1073741824 ==J Jump== @@ -285,8 +290,8 @@ register_v0 = 1 ==JALR Jump and link register== -ORI $5,$0,0x001C LUI $5,0xBFC0 +ORI $5,$5,0x001C JALR $4,$5 NOP ADDIU $2,$2,1 @@ -295,8 +300,8 @@ NOP ORI $2,$0,1 JR $4 -3405001C 3C05BCF0 +34A5001C 00A02009 00000000 24420001 @@ -329,36 +334,46 @@ register_v0 = 2 ==JR Jump register== -ORI $5,$0,0x0014 LUI $5,0xBFC0 +ORI $5,$5,0x0014 JR $5 NOP JR $0 NOP -ORI $2,$0,1 +ORI $2,$0,0xA JR $0 -34050014 -3C05BCF0 +3C05BFC0 +34A50014 00A00008 00000000 00000008 -34020001 +3402000A 00000008 -register_v0 = 1 +register_v0 = 10 + +-Branch Delay slot test + +JR $0 +ORI $2,$0,5 + +00000008 +34020005 + +register_v0 = 5 ==LB Load byte== -ORI $4,$0,0x1003 -LB $2,3($4) +ORI $4,$0,0x1001 JR $0 +LB $2,5($4) -Instruction Hex -34041003 -80820003 +34041001 00000008 +80820005 -Memory Hex @@ -367,94 +382,94 @@ JR $0 00000000 00000000 -register_v0 = 0xFFFFFF8A +register_v0 = 0xFFFFFF8A / 4294967178 ==LBU Load byte unsigned== -ORI $4,$0,0x1003 -LBU $2,3($4) -JR $0 - --Instruction Hex - -34041003 -90820003 -00000008 - --Memory Hex - -00000000 -008A0000 -00000000 -00000000 - -register_v0 = 0x0000008A - -==LH Load half-word== - -ORI $4,$0,0x1003 -LH $2,4($4) -JR $0 - --Instruction Hex - -34041003 -84820004 -00000008 - --Memory Hex - -00000000 -00008123 -00000000 -00000000 - -register_v0 = 0xFFFF8123 - -==LHU Load half-word unsigned== - -ORI $4,$0,0x1003 -LHU $2,4($4) -JR $0 - --Instruction Hex - -34041003 -94820004 -00000008 - --Memory Hex - -00000000 -00008123 -00000000 -00000000 - -register_v0 = 0x00008123 - -==LUI Load upper immediate== - -ORI $2,$0,0x5678 -LUI $2,0x1234 -JR $0 - -34045678 -3C021234 -00000008 - -register_v0 = 0x12345678 - -==LW Load word== - ORI $4,$0,0x1002 -LW $2, 2($4) JR $0 +LBU $2,4($4) -Instruction Hex 34041002 -8C820002 00000008 +90820004 + +-Memory Hex + +00000000 +008A0000 +00000000 +00000000 + +register_v0 = 0x0000008A / 138 + +==LH Load half-word== + +ORI $4,$0,0x1000 +JR $0 +LH $2,4($4) + +-Instruction Hex + +34041003 +00000008 +84820004 + +-Memory Hex + +00000000 +00008123 +00000000 +00000000 + +register_v0 = 0xFFFF8123 / 4294934819 + +==LHU Load half-word unsigned== + +ORI $4,$0,0x1000 +JR $0 +LHU $2,4($4) + +-Instruction Hex + +34041000 +00000008 +94820004 + +-Memory Hex + +00000000 +00008123 +00000000 +00000000 + +register_v0 = 0x00008123 / 33059 + +==LUI Load upper immediate== + +LUI $2,0x1234 +ORI $2,$2,0x5678 +JR $0 + +3C021234 +34425678 +00000008 + +register_v0 = 0x12345678 / 305419896 + +==LW Load word== + +ORI $4,$0,0x1002 +JR $0 +LW $2, 2($4) + +-Instruction Hex + +34041002 +00000008 +8C820002 -Memory Hex @@ -463,21 +478,21 @@ JR $0 00000000 00000000 -register_v0 = 0x12345678 +register_v0 = 0x12345678 / 305419896 ==LWL Load word left== -ORI $4,$0,0x1003 +ORI $4,$0,0x1001 ORI $2,$0,0x5678 -LWL $2,3($4) JR $0 +LWL $2,3($4) -Instruction Hex -34041003 +34041001 34025678 -88820003 00000008 +88820003 -Memory Hex @@ -486,21 +501,21 @@ AAAA1234 00000000 00000000 -register_v0 = 0x12345678 +register_v0 = 0x12345678 / 305419896 ==LWR Load word right== -ORI $4,$0,0x1003 LUI $2,0x1234 -LWR $2,2($4) +ORI $4,$0,0x1002 JR $0 +LWR $2,3($4) -Instruction Hex -34041003 3C021234 -98820002 +34041002 00000008 +98820003 -Memory Hex @@ -509,56 +524,335 @@ JR $0 00000000 00000000 -register_v0 = 0x12345678 +register_v0 = 0x12345678 / 305419896 -// DIVU Divide unsigned +==MTHI Move to HI== -// DIV Divide +ori $4, $0, 5 +mthi $4 +mfhi $2 +jr $0 -//MFHI Move from Hi +34040005 +00800011 +00001010 +00000008 -//MFLO Move from lo +register_v0 = 5 -//MTHI Move to HI +==MTLO Move to LO== -//MTLO Move to LO +ori $4, $0, 5 +mtlo $4 +mflo $2 +jr $0 -//MULT Multiply** +34040005 +00800013 +00001012 +00000008 -//MULTU Multiply unsigned** +register_v0 = 5 -//OR Bitwise or +==MULT Multiply== -//ORI Bitwise or immediate +ori $4, $0, 4 +ori $5, $0, 3 +mult $4, $5 +mflo $2 +jr $0 -//SB Store byte +34040004 +34050003 +00850018 +00001012 +00000008 -//SH Store half-word** +register_v0 = 12 -//SLL Shift left logical +==MULTU Multiply unsigned== -//SLLV Shift left logical variable +ori $4, $0, 4 +ori $5, $0, 3 +multu $4, $5 +mflo $2 +jr $0 -//SLT Set on less than (signed) +34040004 +34050003 +00850019 +00001012 +00000008 -//SLTI Set on less than immediate (signed) +register_v0 = 12 -//SLTIU Set on less than immediate unsigned +==OR Bitwise or== -//SLTU Set on less than unsigned +ori $4, $0, 5 +ori $5, $0, 3 +jr $0 +or $2, $4, $5 -//SRA Shift right arithmetic +34040005 +34050003 +00000008 +00851025 -//SRAV Shift right arithmetic +register_v0 = 7 -//SRL Shift right logical +==ORI Bitwise or immediate== -//SRLV Shift right logical variable +ori $4, $0, 0xFFFF +ori $5, $0, 0x1234 +jr $0 +or $2, $4, $5 -//SUBU Subtract unsigned +3404FFFF +34051234 +00851025 +00000008 -//SW Store word +register_v0 = 65535 -//XOR Bitwise exclusive or +==SB Store byte== -//XORI Bitwise exclusive or immediate +lui $4, 0x1234 +ori $4, $0, 0x5678 +lui $5, 0xBFC0 +ori $5, $0, 0x001C +sb $4, 0($5) +lb $2, 0($5) +jr $0 + +3C041234 +34045678 +3C05BFC0 +3405001C +A0A40000 +80A20000 +00000008 + +register_v0 = 0x00000078 + +==SH Store half-word== + +lui $4, 0x1234 +ori $4, $0, 0x5678 +lui $5, 0xBFC0 +ori $5, $0, 0x001C +sh $4, 0($5) +lh $2, 0($5) +jr $0 + +3C041234 +34045678 +3C05BFC0 +3405001C +A4A40000 +84A40000 +00000008 + +register_v0 = 0x00005678 + +==SLL Shift left logical== + +ori $4,$0,3 +jr $0 +sll $2,$4,2 + + +34040003 +00000008 +00041080 + +register_v0 = 12 + +==SLLV Shift left logical variable== + +ori $4,$0,2 +ori $5,$0,3 +jr $0 +sllv $2,$5,$4 + +34040002 +34050003 +00000008 +00851004 + +register_v0 = 12 + +==SLT Set on less than (signed)== + +ORI $4 $zero 0xFFFF +ORI $5 $zero 0x000B +jr $0 +SLT $2 $4 $5 + +3404FFFF +3405000B +00000008 +0085102A + +register_v0 = 0 + +==SLTI Set on less than immediate (signed)== + +ori $4, $0, 10 +jr $0 +slti $2, $4, 9 + +3404000a +00000008 +28820009 + +register_v0 = 0 + +==SLTIU Set on less than immediate unsigned== + +ori $4, $0, 10 +jr $0 +sltiu $2, $4, 9 + +3404000a +00000008 +2c820009 + +register_v0 = 0 + +==SLTU Set on less than unsigned== + +ori $4, $0, 10 +ori $5, $0, 9 +jr $0 +sltu $2, $4, $5 + +3404000a +34050009 +00000008 +0085102b + +register_v0 = 0 + +==SRA Shift right arithmetic== + +lui $5 $0,0xF000 +jr $0 +srav $2,$5,2 + +3C05F000 +00000008 +00051083 + +register_v0 = 0xFC000000 / 4227858432 + +==SRAV Shift right arithmetic variable== + +ori $4,$0,2 +lui $5, 0xF000 +jr $0 +srav $2,$5,$4 + +34040002 +3C05F000 +00000008 +00851007 + +register_v0 = 0xFC000000 / 4227858432 + +==SRL Shift right logical== + +ori $4,$0,16 +jr $0 +srl $2,$4,2 + +34040010 +00000008 +00041082 + +register_v0 = 4 + +==SRLV Shift right logical variable== + +ori $4,$0,2 +ori $5,$0,16 +jr $0 +srlv $2,$5,$4 + +34040002 +34050010 +00000008 +00851006 + +register_v0 = 4 + +==SUBU Subtract unsigned== + +ori $4,$0,5 +ori $5,$0,3 +jr $0 +subu $2,$4,$5 + +34040005 +34050003 +00000008 +00851023 + +register_v0 = 2 + +==SW Store word== + +ori $4, $0, 0xFFFF +ori $5, $0, 0x1008 +sw $4, 4($5) +lw $2, 4($5) +jr $0 + +3404FFFF +34051008 +ACA40004 +8CA20004 +00000008 + +register_v0 = 0x0000FFFF / 65535 + +-Negative Offset + +ori $4, $0, 0xFFFF +ori $5, $0, 0x1008 +sw $4, -4($5) +lw $2, -4($5) +jr $0 + +3404FFFF +34051008 +ACA4FFFC +8CA2FFFC +00000008 + +register_v0 = 0x0000FFFF / 65535 + +==XOR Bitwise exclusive or== + +ori $4, $0, 5 +ori $5, $0, 2 +jr $0 +xor $2, $4, $5 + +34040005 +34050002 +00000008 +00851026 + +register_v0 = 7 + +==XORI Bitwise exclusive or immediate== + +ori $4,$0,5 +jr $0 +xori $2,$4,0x000F + +34040005 +00000008 +3882000F + +register_v0 = 10 diff --git a/structure.png b/reference/structure.png similarity index 100% rename from structure.png rename to reference/structure.png diff --git a/test/test_mips_cpu_harvard.sh b/test/test_mips_cpu_harvard.sh index 19cb6b7..e5cd348 100755 --- a/test/test_mips_cpu_harvard.sh +++ b/test/test_mips_cpu_harvard.sh @@ -25,7 +25,7 @@ then -s mips_cpu_harvard_tb \ -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \ -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \ - -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \ + -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\ ${SRC} 2> /dev/null ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${DIR}/${TESTCASE}.log.txt)" > ./inputs/${DIR}/${TESTCASE}.out.txt; # register v0 output to compare with reference @@ -46,7 +46,7 @@ else -s mips_cpu_harvard_tb \ -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \ -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ - -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \ + -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\ ${SRC} 2> /dev/null ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference diff --git a/rtl/mips_cpu_memory.v b/testbench/mips_cpu_memory.v similarity index 100% rename from rtl/mips_cpu_memory.v rename to testbench/mips_cpu_memory.v