From ad68ab0974e2d6a743d2228f75780ee1413edc70 Mon Sep 17 00:00:00 2001 From: jl7719 Date: Wed, 16 Dec 2020 12:29:22 +0000 Subject: [PATCH] Debugging and debugging PC, Jump instr, branches --- inputs/addiu/addiu-2.ref.txt | 1 + inputs/addiu/addiu-2.txt | 2 ++ inputs/beq/beq-2.ref.txt | 1 + inputs/beq/beq-2.txt | 8 ++++++++ inputs/j/j-1.txt | 2 +- inputs/jal/jal-1.txt | 2 +- inputs/jalr/jalr-1.txt | 2 +- inputs/jalr/jalr-2.ref.txt | 1 + inputs/jalr/jalr-2.txt | 6 ++++++ inputs/jr/jr-1.ref.txt | 2 +- inputs/jr/jr-1.txt | 2 +- inputs/jr/jr-2.ref.txt | 1 + inputs/jr/jr-2.txt | 2 ++ reference.txt | 18 ++++++++---------- rtl/mips_cpu_alu.v | 1 + rtl/mips_cpu_control.v | 3 ++- rtl/mips_cpu_pc.v | 14 ++++++++------ test/test_mips_cpu_custom.sh | 6 +++--- 18 files changed, 49 insertions(+), 25 deletions(-) create mode 100644 inputs/addiu/addiu-2.ref.txt create mode 100644 inputs/addiu/addiu-2.txt create mode 100644 inputs/beq/beq-2.ref.txt create mode 100644 inputs/beq/beq-2.txt create mode 100644 inputs/jalr/jalr-2.ref.txt create mode 100644 inputs/jalr/jalr-2.txt create mode 100644 inputs/jr/jr-2.ref.txt create mode 100644 inputs/jr/jr-2.txt diff --git a/inputs/addiu/addiu-2.ref.txt b/inputs/addiu/addiu-2.ref.txt new file mode 100644 index 0000000..9a03714 --- /dev/null +++ b/inputs/addiu/addiu-2.ref.txt @@ -0,0 +1 @@ +10 \ No newline at end of file diff --git a/inputs/addiu/addiu-2.txt b/inputs/addiu/addiu-2.txt new file mode 100644 index 0000000..664859c --- /dev/null +++ b/inputs/addiu/addiu-2.txt @@ -0,0 +1,2 @@ +2442000A +00000008 \ No newline at end of file diff --git a/inputs/beq/beq-2.ref.txt b/inputs/beq/beq-2.ref.txt new file mode 100644 index 0000000..bf0d87a --- /dev/null +++ b/inputs/beq/beq-2.ref.txt @@ -0,0 +1 @@ +4 \ No newline at end of file diff --git a/inputs/beq/beq-2.txt b/inputs/beq/beq-2.txt new file mode 100644 index 0000000..07e24de --- /dev/null +++ b/inputs/beq/beq-2.txt @@ -0,0 +1,8 @@ +34040005 +34050005 +10850003 +34020005 +00000008 +00000000 +2442000A +00000008 \ No newline at end of file diff --git a/inputs/j/j-1.txt b/inputs/j/j-1.txt index 0043747..65aa6d3 100644 --- a/inputs/j/j-1.txt +++ b/inputs/j/j-1.txt @@ -1,4 +1,4 @@ -08000004 +0BF00004 00000000 00000008 00000000 diff --git a/inputs/jal/jal-1.txt b/inputs/jal/jal-1.txt index f2e38d0..2f9d6ca 100644 --- a/inputs/jal/jal-1.txt +++ b/inputs/jal/jal-1.txt @@ -1,4 +1,4 @@ -0C000005 +0FF00005 00000000 24420001 00000008 diff --git a/inputs/jalr/jalr-1.txt b/inputs/jalr/jalr-1.txt index fc2bb83..2c5bb1c 100644 --- a/inputs/jalr/jalr-1.txt +++ b/inputs/jalr/jalr-1.txt @@ -1,5 +1,5 @@ 3C05BCF0 -3405001C +34A5001C 00A02009 00000000 24420001 diff --git a/inputs/jalr/jalr-2.ref.txt b/inputs/jalr/jalr-2.ref.txt new file mode 100644 index 0000000..65d2cb8 --- /dev/null +++ b/inputs/jalr/jalr-2.ref.txt @@ -0,0 +1 @@ +3217031184 \ No newline at end of file diff --git a/inputs/jalr/jalr-2.txt b/inputs/jalr/jalr-2.txt new file mode 100644 index 0000000..6cb84fc --- /dev/null +++ b/inputs/jalr/jalr-2.txt @@ -0,0 +1,6 @@ +3C05BCF0 +34A50014 +00A01009 +00000000 +00000000 +00000008 \ No newline at end of file diff --git a/inputs/jr/jr-1.ref.txt b/inputs/jr/jr-1.ref.txt index 56a6051..9a03714 100644 --- a/inputs/jr/jr-1.ref.txt +++ b/inputs/jr/jr-1.ref.txt @@ -1 +1 @@ -1 \ No newline at end of file +10 \ No newline at end of file diff --git a/inputs/jr/jr-1.txt b/inputs/jr/jr-1.txt index 79610db..a64f24a 100644 --- a/inputs/jr/jr-1.txt +++ b/inputs/jr/jr-1.txt @@ -1,5 +1,5 @@ 3C05BFC0 -34050014 +34A50014 00A00008 00000000 00000008 diff --git a/inputs/jr/jr-2.ref.txt b/inputs/jr/jr-2.ref.txt new file mode 100644 index 0000000..7813681 --- /dev/null +++ b/inputs/jr/jr-2.ref.txt @@ -0,0 +1 @@ +5 \ No newline at end of file diff --git a/inputs/jr/jr-2.txt b/inputs/jr/jr-2.txt new file mode 100644 index 0000000..30eb859 --- /dev/null +++ b/inputs/jr/jr-2.txt @@ -0,0 +1,2 @@ +00000008 +34020005 \ No newline at end of file diff --git a/reference.txt b/reference.txt index 2d6129f..493a0f9 100644 --- a/reference.txt +++ b/reference.txt @@ -356,20 +356,18 @@ JR $5 NOP JR $0 NOP -ORI $2,$0,1 +ORI $2,$0,0xA JR $0 -BFC00014 -0,4,8,c,10,14 -3C05BFC0 0 -34050014 4 -00A00008 8 -00000000 c -00000008 10 -34020001 14 +3C05BFC0 +34A50014 +00A00008 +00000000 +00000008 +3402000A 00000008 -register_v0 = 1 +register_v0 = 10 ==LB Load byte== diff --git a/rtl/mips_cpu_alu.v b/rtl/mips_cpu_alu.v index 11e564b..bc7fefe 100644 --- a/rtl/mips_cpu_alu.v +++ b/rtl/mips_cpu_alu.v @@ -135,6 +135,7 @@ end SLL: begin ALURes = B << shamt; + $display("ALURES SLL: %h", ALURes); end SLLV: begin diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v index a668eed..d11886c 100644 --- a/rtl/mips_cpu_control.v +++ b/rtl/mips_cpu_control.v @@ -200,6 +200,7 @@ always @(*) begin Ctrlshamt = Instr[10:6];// Shift amount piped in from the instruction end else if(op == LUI)begin Ctrlshamt = 5'd16;//Used specifically to implement LUI as the instruction itslef does not include shamt + $display("LUI SHIFTING"); end else begin Ctrlshamt = 5'bxxxxx;end //CtrlMemWrite logic @@ -223,7 +224,7 @@ always @(*) begin end else begin CtrlALUSrc = 1'bx;end //CtrlRegWrite logic - if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) begin + if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin CtrlRegWrite = 1;//The Registers are Write Enabled $display("OPcode mflo: %h", op); end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled diff --git a/rtl/mips_cpu_pc.v b/rtl/mips_cpu_pc.v index 7531c00..e6bee1b 100644 --- a/rtl/mips_cpu_pc.v +++ b/rtl/mips_cpu_pc.v @@ -8,11 +8,12 @@ module mips_cpu_pc( output logic active ); -reg [31:0] pc_next, pc_lit_next; +reg [31:0] pc_next, pc_lit_next, pc_next_next; initial begin pc_out = 32'hBFC00000; pc_next = pc_out + 32'd4; + end assign pc_lit_next = pc_out + 32'd4; @@ -26,27 +27,28 @@ always_ff @(posedge clk) begin active <= 0; end pc_out <= pc_next; + pc_next <= pc_next_next; end end - always @(*) begin case(pc_ctrl) 2'd1: begin // Branch - pc_next = pc_out + 32'd4 + {{14{instr[15]}},instr[15:0],2'b00}; + pc_next_next = pc_out + 32'd4 + {{14{instr[15]}},instr[15:0],2'b00}; end 2'd2: begin // Jump - pc_next = {pc_lit_next[31:28], instr[25:0], 2'b00}; + pc_next_next = {pc_lit_next[31:28], instr[25:0], 2'b00}; $display("JUMPING"); $display("pc_lit_next: %h", pc_lit_next[31:28]); $display("instr: %b", instr[25:0]); $display("%h",pc_next); end 2'd3: begin // Jump using Register - pc_next = reg_readdata; + pc_next_next = reg_readdata; + $display("REGREADEADTAATATAT %h", reg_readdata); end default: begin - pc_next = pc_out + 32'd4; + pc_next_next = pc_out + 32'd4; end endcase end diff --git a/test/test_mips_cpu_custom.sh b/test/test_mips_cpu_custom.sh index 32858e4..125930a 100755 --- a/test/test_mips_cpu_custom.sh +++ b/test/test_mips_cpu_custom.sh @@ -24,14 +24,14 @@ #./test/test_mips_cpu_harvard.sh rtl bgezal #Place return address thing how?? ./test/test_mips_cpu_harvard.sh rtl bgtz #Pass ./test/test_mips_cpu_harvard.sh rtl blez #Pass -./test/test_mips_cpu_harvard.sh rtl bltz #Probably fails due to jump register thing? +./test/test_mips_cpu_harvard.sh rtl bltz #Pass ./test/test_mips_cpu_harvard.sh rtl bltzal #Pass ./test/test_mips_cpu_harvard.sh rtl bne #Pass # jumps -#./test/test_mips_cpu_harvard.sh rtl j #Need new testcase +./test/test_mips_cpu_harvard.sh rtl j #Pass #./test/test_mips_cpu_harvard.sh rtl jalr #Again how to link? -#./test/test_mips_cpu_harvard.sh rtl jal #how to link? +./test/test_mips_cpu_harvard.sh rtl jal #Pass ./test/test_mips_cpu_harvard.sh rtl jr #Pass # shift