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Updated ALU
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@ -1,238 +1,202 @@
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module mips_cpu_alu(
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input signed logic[31:0] A, B,//alu_in1, alu_in2 -The two ALU inputs
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input logic [5:0] ALUFlags, //Output from ALU control - 6bits as there are 48 different instructions in our ISA that we need to implement
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/* The ALU Flags is 6 bits for now update when reduced */
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output logic Cond, //IF condition is met Cond is asserted
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output logic[31:0] ALUOut, // The ouput of the ALU
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input logic[4:0] shamt
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input signed logic[31:0] A, //Bus A - Input from the Readdata1 output from the reg file which corresponds to rs.
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input signed logic[31:0] B, //Bus B - Input from the Readdata2 output from the reg file which corresponds to rt.
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input logic [4:0] ALUOp, // 5-bit output from Control that tells the alu what operation to do from a list of 20 distinct alu operations(see below).
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input logic [4:0] shamt, //5-bit input used to specify shift amount for shift operations. Taken directly from the R-type instruction (Non-Variable) or from
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output logic ALUCond, //If a relevant condition is met, this output goes high(Active High). Note: Relevant as in related to current condition being tested.
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output signed logic[31:0] ALURes, // The ouput of the ALU
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);
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/*
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reg [31:0] SignExtend, ZeroExtend;
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// Instructions commented out have been accounted for
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Alu Operations:
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-Manipulation Operations: The perform an operation on a value(s).
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- Addition
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- Subtraction
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- Multiplication
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- Division
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- Bitwise AND
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- Bitwise OR
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- Bitwise XOR
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- Shift Left Logical
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- Shift Left Logical Variable
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- Shift Right Logical
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- Shift Right Logical Variable
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- Shift Right Arithmetic
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- Shift Right Arithmetic Variable
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-Condtional Check Operations: They check conditions.
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- Equality (=)
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- Less Than (<)
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- Less Than or Equal To (<=)
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- Greater Than (>)
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- Greater Than or Equal to (>=)
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- Negative Equality(=/=)
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-Implementation Operation:
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- Pass-through (Used to implement MTHI and MTLO, as these instructions do not need the ALU but the alu is in the pathway to the regfile, so the register value simply passes through.)
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/* Using an enum to define constants */
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//typedef enum logic[5:0] {
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//ADDIU = 6'd0, //Add immediate unsigned (no overflow)
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//ADDU = 6'd1, //Add unsigned (no overflow)
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//AND = 6'd2, //Bitwise and
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//ANDI = 6'd3, //Bitwise and immediate
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//BEQ = 6'd4, //Branch on equal
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//BGEZ = 6'd5, //Branch on greater than or equal to zero
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//BGEZAL = 6'd6, //Branch on non-negative (>=0) and link
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//BGTZ = 6'd7, //Branch on greater than zero
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//BLEZ = 6'd8, //Branch on less than or equal to zero
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//BLTZ = 6'd9, //Branch on less than zero
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//BLTZAL = 6'd10, //Branch on less than zero and link
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//BNE = 6'd11, //Branch on not equal
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//DIV = 6'd12, //Divide
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//DIVU = 6'd13, //Divide unsigned
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//LB = 6'd18, //Load byte
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//LBU = 6'd19, //Load byte unsigned
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//LH = 6'd20, //Load half-word
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//LHU = 6'd21, //Load half-word unsigned
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//LUI = 6'd22, //Load upper immediate
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LW = 6'd23, //Load word
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LWL = 6'd24, //Load word left
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LWR = 6'd25, //Load word right
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MTHI = 6'd26, //Move to HI
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MTLO = 6'd27, //Move to LO
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//MULT = 6'd28, //Multiply
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//MULTU = 6'd29, //Multiply unsigned
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//OR = 6'd30, //Bitwise or
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//ORI = 6'd31, //Bitwise or immediate
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//SB = 6'd32, //Store byte
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//SH = 6'd33, //Store half-word
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//SLL = 6'd34, //Shift left logical
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//SLLV = 6'd35, //Shift left logical variable
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//SLT = 6'd36, //Set on less than (signed)
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//SLTI = 6'd37, //Set on less than immediate (signed)
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//SLTIU = 6'd38, //Set on less than immediate unsigned
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//SLTU = 6'd39, //Set on less than unsigned
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//SRA = 6'd40, //Shift right arithmetic
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// SRAV = 6'd41, //Shift right arithmetic
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//SRL = 6'd42, //Shift right logical
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//SRLV = 6'd43, //Shift right logical variable
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//SUBU = 6'd44, //Subtract unsigned
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//SW = 6'd45, //Store word
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//XOR = 6'd46, //Bitwise exclusive or
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//XORI = 6'd47, //Bitwise exclusive or immediate
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//} ALUFlags;
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*/
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/* This is how I believe our ctrl flags should be arranged */
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typedef enum logic [4:0]{ //Enum list to use words instead of numbers when refering to operations.
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typedef enum logic [6:0]{
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ADD = 5'd0,
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SUB = 5'd1,
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MUL = 5'd2,
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DIV = 5'd3,
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AND = 5'd4,
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OR = 5'd5,
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XOR = 5'd6,
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SLL = 5'd7,
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SLLV = 5'd8,
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SRL = 5'd9,
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SRLV = 5'd10,
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SRA = 5'd11,
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SRAV = 5'd12,
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EQ = 5'd13,
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LES = 5'd14,
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LEQ = 5'd15,
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GRT = 5'd16,
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GEQ = 5'd17,
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NEQ = 5'd18,
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PAS = 5'd19
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} Ops;
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Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming errors, as a result of enum implemetnation quirks.
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assign ALUOps = ALUOp
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always_comb begin
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} ALUFlags;
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always_comb
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begin
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SignExtend = {{16{immediate[15]}}, immediate};
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ZeroExtend = {{16{1'b0}}, immediate};
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case(ALUFlags)
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case(ALUOps)
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ADD: begin
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ALUOut = A + B; // is it = or <= ??
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ALURes = A + B;
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end
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SUB: begin
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ALUOut = A - B;
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ALURes = A - B;
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end
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MULT: begin
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ALUOut = A * B;
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MUL: begin
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ALURes = A * B;
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end
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DIV: begin
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ALUOut = A / B;
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ALURes = A / B;
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end
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XOR: begin
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ALUOut = A^B;
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AND: begin
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ALUOut = A & B;
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end
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OR: begin
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ALUOut = A | B;
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end
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SLL: begin
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ALUOut = B << shamt; //Shamt is instruction read data [10:6]
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XOR: begin
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ALUOut = A^B;
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end
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SRL: begin
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ALUOut = B >> shamt; //Shamt is instruction read data [10:6]
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SLL: begin
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ALUOut = B << shamt;
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end
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SLLV: begin
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ALUOut = B << A;
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end
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SRL: begin
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ALUOut = B >> shamt;
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end
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SRLV: begin
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ALUOut = B >> A;
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end
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AND: begin
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ALUOut = A & B;
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end
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//kjfdhlkjsfhlsajdflskajflsjflskjf;lksjf;jsf;kl
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BEQ: begin
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if A == B begin
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Cond = 1;
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end
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else begin
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Cond = 0;
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end
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end
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BGEZ: begin
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if A>=0 begin
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Cond = 1;
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end
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else begin
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Cond = 0;
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end
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end
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BGEZAL: begin
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if A>=0 begin
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Cond = 1;
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end
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else begin
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Cond = 0;
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end
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end
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BGTZ: begin
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if A>0 begin
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Cond = 1;
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end
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else begin
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Cond = 0;
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end
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end
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BLEZ: begin
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if A<=0 begin
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Cond = 1;
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end
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else begin
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Cond = 0;
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end
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end
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BNE: begin
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if A<=0 begin
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Cond = 1;
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end
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else begin
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Cond = 0;
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end
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end
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LB: begin
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ALUOut = A + SignExtend;
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end
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LBU: begin
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ALUOut = A + ZeroExtend;
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end
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LH: begin
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ALUOut = A + SignExtend;
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end
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LHU: begin
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ALUOut = A + ZeroExtend;
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end
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LUI: begin
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ALUOut = {immediate, {16{1'b0}}};
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end
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SB: begin
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ALUOut = A + SignExtend;
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end
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SH: begin
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ALUOut = A + SignExtend;
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end
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SLT: begin
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ALUOut = $signed(A) < $signed(B) ? 1 : 0;
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end
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SLTU: begin
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ALUOut = A < B ? 1 : 0;
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end
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SRA: begin
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ALUOut = $signed($signed(B) >>> shamt);
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ALUOut = B >>> shamt;
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end
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SRAV: begin
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ALUOut = $signed($signed(B) >>> A);
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ALUOut = B >>> A;
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end
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SW: begin
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ALUOut = A + SignExtend;
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EQ: begin
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if A == B begin
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ALUCond = 1;
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end
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else begin
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ALUCond = 0;
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end
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end
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LES: begin
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if A < B begin
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ALUCond = 1;
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end
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else begin
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ALUCond = 0;
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end
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end
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LEQ: begin
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if A <= B begin
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ALUCond = 1;
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end
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else begin
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ALUCond = 0;
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end
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end
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LEQ: begin
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if A <= B begin
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ALUCond = 1;
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end
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else begin
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ALUCond = 0;
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end
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end
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GRT: begin
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if A > B begin
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ALUCond = 1;
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end
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else begin
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ALUCond = 0;
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end
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end
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GEQ: begin
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if A >= B begin
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ALUCond = 1;
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end
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else begin
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ALUCond = 0;
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end
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end
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NEQ: begin
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if A != B begin
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ALUCond = 1;
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end
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else begin
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ALUCond = 0;
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end
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end
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PAS: begin
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ALURes = A;
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end
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endcase
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end
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endmodule
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