diff --git a/inputs/div.ref.txt b/inputs/div.ref.txt
new file mode 100644
index 0000000..e440e5c
--- /dev/null
+++ b/inputs/div.ref.txt
@@ -0,0 +1 @@
+3
\ No newline at end of file
diff --git a/inputs/j.ref.txt b/inputs/j.ref.txt
index 56a6051..c793025 100644
--- a/inputs/j.ref.txt
+++ b/inputs/j.ref.txt
@@ -1 +1 @@
-1
\ No newline at end of file
+7
\ No newline at end of file
diff --git a/inputs/j.txt b/inputs/j.txt
index 0043747..8955259 100644
--- a/inputs/j.txt
+++ b/inputs/j.txt
@@ -1,6 +1,11 @@
-08000004
+083F0004
 00000000
+00000000
+00000000
+00000000
+
 00000008
 00000000
-34020001
-00000008
\ No newline at end of file
+34020007
+00000008
+
diff --git a/inputs/jr.ref.txt b/inputs/jr.ref.txt
index 56a6051..19c7bdb 100644
--- a/inputs/jr.ref.txt
+++ b/inputs/jr.ref.txt
@@ -1 +1 @@
-1
\ No newline at end of file
+16
\ No newline at end of file
diff --git a/inputs/jr.txt b/inputs/jr.txt
index b2a8045..88a1c8f 100644
--- a/inputs/jr.txt
+++ b/inputs/jr.txt
@@ -1,7 +1,7 @@
-34050014
-3C05BCF0
+3C05BFC0
+34A50014
 00A00008
 00000000
 00000008
-34020001
-00000008
\ No newline at end of file
+34020010
+00000008
diff --git a/inputs/lb.data.txt b/inputs/lb.data.txt
index 47c26d6..4f67055 100644
--- a/inputs/lb.data.txt
+++ b/inputs/lb.data.txt
@@ -1,4 +1,4 @@
 00000000
-008A0000
+0000008A
 00000000
 00000000
\ No newline at end of file
diff --git a/inputs/lb.txt b/inputs/lb.txt
index 83898a5..7f80e84 100644
--- a/inputs/lb.txt
+++ b/inputs/lb.txt
@@ -1,3 +1,3 @@
-34041003
-80820003
+34041000
+80820005
 00000008
\ No newline at end of file
diff --git a/inputs/lbu.data.txt b/inputs/lbu.data.txt
index 47c26d6..4f67055 100644
--- a/inputs/lbu.data.txt
+++ b/inputs/lbu.data.txt
@@ -1,4 +1,4 @@
 00000000
-008A0000
+0000008A
 00000000
 00000000
\ No newline at end of file
diff --git a/inputs/lbu.txt b/inputs/lbu.txt
index 06c0f06..5c319dc 100644
--- a/inputs/lbu.txt
+++ b/inputs/lbu.txt
@@ -1,3 +1,3 @@
-34041003
-90820003
+34041000
+90820006
 00000008
\ No newline at end of file
diff --git a/inputs/lh.txt b/inputs/lh.txt
index 3a583e1..aa12925 100644
--- a/inputs/lh.txt
+++ b/inputs/lh.txt
@@ -1,3 +1,3 @@
-34041003
+34041000
 84820004
 00000008
\ No newline at end of file
diff --git a/inputs/lhu.txt b/inputs/lhu.txt
index 54a3692..d8bc6f1 100644
--- a/inputs/lhu.txt
+++ b/inputs/lhu.txt
@@ -1,3 +1,3 @@
-34041003
+34041000
 94820004
 00000008
\ No newline at end of file
diff --git a/inputs/lui.txt b/inputs/lui.txt
index 6c9915e..4a8b509 100644
--- a/inputs/lui.txt
+++ b/inputs/lui.txt
@@ -1,3 +1,3 @@
-34045678
 3C021234
-00000008
\ No newline at end of file
+34425678
+00000008
diff --git a/inputs/lwl.txt b/inputs/lwl.txt
index a62ec0b..c682e96 100644
--- a/inputs/lwl.txt
+++ b/inputs/lwl.txt
@@ -1,4 +1,4 @@
-34041003
+34041001
 34025678
 88820003
 00000008
\ No newline at end of file
diff --git a/inputs/lwr.txt b/inputs/lwr.txt
index 22f33f9..cea76c4 100644
--- a/inputs/lwr.txt
+++ b/inputs/lwr.txt
@@ -1,4 +1,4 @@
-34041003
+34041002
 3C021234
 98820002
 00000008
\ No newline at end of file
diff --git a/inputs/mfhi.ref.txt b/inputs/mfhi.ref.txt
new file mode 100644
index 0000000..e440e5c
--- /dev/null
+++ b/inputs/mfhi.ref.txt
@@ -0,0 +1 @@
+3
\ No newline at end of file
diff --git a/inputs/mflo.ref.txt b/inputs/mflo.ref.txt
new file mode 100644
index 0000000..3cacc0b
--- /dev/null
+++ b/inputs/mflo.ref.txt
@@ -0,0 +1 @@
+12
\ No newline at end of file
diff --git a/inputs/mthi.ref.txt b/inputs/mthi.ref.txt
new file mode 100644
index 0000000..7813681
--- /dev/null
+++ b/inputs/mthi.ref.txt
@@ -0,0 +1 @@
+5
\ No newline at end of file
diff --git a/inputs/mult.ref.txt b/inputs/mult.ref.txt
new file mode 100644
index 0000000..3cacc0b
--- /dev/null
+++ b/inputs/mult.ref.txt
@@ -0,0 +1 @@
+12
\ No newline at end of file
diff --git a/inputs/multu.ref.txt b/inputs/multu.ref.txt
new file mode 100644
index 0000000..3cacc0b
--- /dev/null
+++ b/inputs/multu.ref.txt
@@ -0,0 +1 @@
+12
\ No newline at end of file
diff --git a/inputs/ori.txt b/inputs/ori.txt
index 6b8c243..3cc3faa 100644
--- a/inputs/ori.txt
+++ b/inputs/ori.txt
@@ -1,5 +1,5 @@
-34020008
 00000008
+34020008
 00000000
 00000000
 00000000
diff --git a/inputs/reference/ibrahimreference.txt b/inputs/reference/ibrahimreference.txt
index ddcf491..af79036 100644
--- a/inputs/reference/ibrahimreference.txt
+++ b/inputs/reference/ibrahimreference.txt
@@ -138,15 +138,17 @@ int main(void) {
     int b = -2147483647>>2; #arithemtic shift not logical - feed in 1s (sign extension)
 }
 
-ori $4, $0, 2
-ori $5,$0,-2147483647
+ori $4, $0, 4
+ori $5,$0,0xF000
 srav $2,$5,$4
+SRAv $v0 $a1 $a0
 jr $0
 
 register 0 = -536870912 (first 3 bits high - rest low)
 
-34040002
-34050001
+34040004
+3405F000
+
 ////////
 ///////
 
diff --git a/inputs/reference/reference.txt b/inputs/reference/reference.txt
index ff067cb..b8daeed 100644
--- a/inputs/reference/reference.txt
+++ b/inputs/reference/reference.txt
@@ -267,21 +267,21 @@ register_v0 = 0x40000000
 
 ==J	Jump==
 
-J 4
+J 12
 NOP
 JR $0
 NOP
 ORI $2,$0,1
 JR $0
 
-08000004
+0800000C
 00000000
 00000008
 00000000
-34020001
+3402000A
 00000008
 
-register_v0 = 1
+register_v0 = 10
 
 ==JALR	Jump and link register==
 
@@ -329,24 +329,24 @@ register_v0 = 2
 
 ==JR	Jump register==
 
-ORI $5,$0,0x0014
 LUI $5,0xBFC0  
+ORI $5,$5,0x0014
 JR $5  
 NOP
 JR $0
 NOP
-ORI $2,$0,1
+ORI $2,$0,0x10
 JR $0
 
-34050014
-3C05BCF0
+3C05BFC0
+34A50014
 00A00008
 00000000
 00000008
-34020001
+34020010
 00000008
 
-register_v0 = 1
+register_v0 = 16
 
 ==LB	Load byte==
 
@@ -356,8 +356,8 @@ JR $0
 
 -Instruction Hex
 
-34041003
-80820003
+34041000
+80820006
 00000008
 
 -Memory Hex
@@ -434,12 +434,12 @@ register_v0 = 0x00008123
 
 ==LUI	Load upper immediate==
 
-ORI $2,$0,0x5678
 LUI $2,0x1234
+ORI $2,$2,0x5678
 JR $0
 
-34045678
 3C021234
+34425678
 00000008
 
 register_v0 = 0x12345678
@@ -467,14 +467,14 @@ register_v0 = 0x12345678
 
 ==LWL	Load word left==
 
-ORI $4,$0,0x1003
+ORI $4,$0,0x1001
 ORI $2,$0,0x5678
 LWL  $2,3($4)
 JR $0
 
 -Instruction Hex
 
-34041003
+34041001
 34025678
 88820003
 00000008
@@ -490,14 +490,14 @@ register_v0 = 0x12345678
 
 ==LWR	Load word right==
 
-ORI $4,$0,0x1003
+ORI $4,$0,0x1002
 LUI $2,0x1234
 LWR $2,2($4)
 JR $0
 
 -Instruction Hex
 
-34041003
+34041002
 3C021234
 98820002
 00000008
@@ -559,6 +559,25 @@ register_v0 = 0x12345678
 
 //SW	Store word
 
+ori $4, $0, 0xFFFF  3404FFFF
+ori $5, $0, 0x1008  34051008
+sw $4, 4($5)        ACA40004
+ori $5, $0, 0x100C   3405100C
+lw $2, 0($5)        8CA20000
+jr $0               00000008
+
+ori $4, $0, 0x1234
+ori $5, $0, 0x1008
+sw $4, 0($5)
+lw $2, 0($5)
+jr $0
+
+3404FFFF
+34051008
+ACA40000
+8CA20000
+00000008
+
 //XOR	Bitwise exclusive or
 
 //XORI	Bitwise exclusive or immediate
diff --git a/inputs/sllv.ref.txt b/inputs/sllv.ref.txt
new file mode 100644
index 0000000..3cacc0b
--- /dev/null
+++ b/inputs/sllv.ref.txt
@@ -0,0 +1 @@
+12
\ No newline at end of file
diff --git a/inputs/sllv.txt b/inputs/sllv.txt
index 93c2eb4..d733281 100644
--- a/inputs/sllv.txt
+++ b/inputs/sllv.txt
@@ -1,4 +1,4 @@
 34040002
 34050003
-//////
-//////
\ No newline at end of file
+00851004
+00000008
\ No newline at end of file
diff --git a/inputs/slt.ref.txt b/inputs/slt.ref.txt
new file mode 100644
index 0000000..56a6051
--- /dev/null
+++ b/inputs/slt.ref.txt
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/inputs/slt.txt b/inputs/slt.txt
new file mode 100644
index 0000000..013d035
--- /dev/null
+++ b/inputs/slt.txt
@@ -0,0 +1,4 @@
+3404FFFF
+3405000B
+0085102A
+00000008
\ No newline at end of file
diff --git a/inputs/slti.txt b/inputs/slti.txt
index daf8c51..e48bf85 100644
--- a/inputs/slti.txt
+++ b/inputs/slti.txt
@@ -1,3 +1,3 @@
 3404000a
+00000008
 28820009
-00000008
\ No newline at end of file
diff --git a/inputs/sltiu.txt b/inputs/sltiu.txt
index a601fcc..4828fa9 100644
--- a/inputs/sltiu.txt
+++ b/inputs/sltiu.txt
@@ -1,3 +1,4 @@
 3404000a
-2c820009
 00000008
+2c820009
+
diff --git a/inputs/sra.ref.txt b/inputs/sra.ref.txt
index b5f2596..dff79fe 100644
--- a/inputs/sra.ref.txt
+++ b/inputs/sra.ref.txt
@@ -1 +1 @@
--536870912
\ No newline at end of file
+4294967040
\ No newline at end of file
diff --git a/inputs/sra.txt b/inputs/sra.txt
index 431e720..3a16f78 100644
--- a/inputs/sra.txt
+++ b/inputs/sra.txt
@@ -1,3 +1,3 @@
-3404000C
-00041083
+3404F000
+00041103
 00000008
diff --git a/inputs/srav.ref.txt b/inputs/srav.ref.txt
index e69de29..dff79fe 100644
--- a/inputs/srav.ref.txt
+++ b/inputs/srav.ref.txt
@@ -0,0 +1 @@
+4294967040
\ No newline at end of file
diff --git a/inputs/srav.txt b/inputs/srav.txt
index bb14f29..1a39374 100644
--- a/inputs/srav.txt
+++ b/inputs/srav.txt
@@ -1,4 +1,4 @@
-34040002
-34050001
-////////
-///////
\ No newline at end of file
+34040004
+3405F000
+00851007
+00000008
\ No newline at end of file
diff --git a/inputs/srlv.ref.txt b/inputs/srlv.ref.txt
new file mode 100644
index 0000000..bf0d87a
--- /dev/null
+++ b/inputs/srlv.ref.txt
@@ -0,0 +1 @@
+4
\ No newline at end of file
diff --git a/inputs/srlv.txt b/inputs/srlv.txt
index fa1b6a4..ae99941 100644
--- a/inputs/srlv.txt
+++ b/inputs/srlv.txt
@@ -1,4 +1,4 @@
 34040002
 34050010
-//////
-//////
\ No newline at end of file
+00851006
+00000008
\ No newline at end of file
diff --git a/inputs/sw.ref.txt b/inputs/sw.ref.txt
new file mode 100644
index 0000000..b7bf491
--- /dev/null
+++ b/inputs/sw.ref.txt
@@ -0,0 +1 @@
+4294967295
\ No newline at end of file
diff --git a/inputs/sw.txt b/inputs/sw.txt
index cdba78c..6e0bac8 100644
--- a/inputs/sw.txt
+++ b/inputs/sw.txt
@@ -1,4 +1,5 @@
-34040005
-34050001
-aca40001
+3404FFFF
+34051008
+ACA40000
+8CA20000
 00000008
\ No newline at end of file
diff --git a/rtl/mips_cpu_alu.v b/rtl/mips_cpu_alu.v
index 458b957..3001548 100644
--- a/rtl/mips_cpu_alu.v
+++ b/rtl/mips_cpu_alu.v
@@ -123,11 +123,11 @@ assign ALUOps = ALUOp;
       end
 
       SRA: begin
-          ALURes = B >>> shamt;
+          ALURes = $signed(B) >>> shamt;
       end
 
       SRAV: begin
-          ALURes = B >>> A;
+          ALURes = $signed(B) >>> A;
       end
    
       EQ: begin
diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v
index 0d22916..c4f0322 100644
--- a/rtl/mips_cpu_control.v
+++ b/rtl/mips_cpu_control.v
@@ -99,6 +99,7 @@ always @(*) begin
         CtrlPC = 2'd1; // Branches - Jumps relative to PC
     end else if((op==J) || (op==JAL))begin
         CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
+        $display("Jump PC Ctrl");
     end else if((op==SPECIAL)&&(funct==JR) || (funct==JALR))begin
         CtrlPC = 2'd3; // Jumps using Register.
         //$display("Ctrl PC Jump Register");
@@ -141,6 +142,7 @@ always @(*) begin
         CtrlALUOp = 5'd23;//DIVU from ALUOps
     end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
         CtrlALUOp = 5'd0;//ADD from ALUOps
+        $display("LB IN CONTROL");
     end else if(op==LUI)begin
         CtrlALUOp = 5'd7;//SLL from ALUOps
     end else if((op==SPECIAL)&&((funct==MTHI) || (funct==MTLO)))begin
@@ -156,8 +158,10 @@ always @(*) begin
         $display("ALU Op = 7 (SLL)");
     end else if((op==SPECIAL)&&(funct==SLLV))begin
         CtrlALUOp = 5'd8;//SLLV from ALUOps
+        $display("ALU Op = 9 (SLLV)");
     end else if((op==SPECIAL)&&(funct==SRA))begin
         CtrlALUOp = 5'd11;//SRA from ALUOps
+        $display("ALU Op = 11 (SRA)");
     end else if((op==SPECIAL)&&(funct==SRAV))begin
         CtrlALUOp = 5'd12;//SRAV from ALUOps
     end else if((op==SPECIAL)&&(funct==SRL))begin
@@ -167,8 +171,10 @@ always @(*) begin
         CtrlALUOp = 5'd10;//SRLV from ALUOps
     end else if((op==SLTI) || ((op==SPECIAL)&&(funct==SLT)))begin
         CtrlALUOp = 5'd20;//SLT from ALUOps
+        $display("ALU Op = 20 (SLT/SLTI)");
     end else if((op==SLTIU) || ((op==SPECIAL)&&(funct==SLTU)))begin
         CtrlALUOp = 5'd21;//SLTU from ALUOps
+        $display("ALU Op = 21 (SLTU/SLTIU)");
     end else if((op==SPECIAL)&&(funct==SUBU))begin
         CtrlALUOp = 5'd1;//SUB from ALUOps
     end else if((op==XORI) || ((op==SPECIAL)&&(funct==XOR)))begin
@@ -193,13 +199,13 @@ always @(*) begin
     //CtrlALUSrc logic
     if((op==ADDIU) || (op==ANDI) || (op==LUI) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
         CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0]
-    end else if((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL))))begin 
+    end else if((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL))))begin 
         CtrlALUSrc = 0;///ALU Bus B is fed from rt.
     end else begin CtrlALUSrc = 1'bx;end
        
     //CtrlRegWrite logic
-    if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) begin
+    if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU)  || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) begin
         CtrlRegWrite = 1;//The Registers are Write Enabled
     end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
 end
-endmodule
+endmodule
\ No newline at end of file
diff --git a/rtl/mips_cpu_memory.v b/rtl/mips_cpu_memory.v
index e274292..fa6ce75 100644
--- a/rtl/mips_cpu_memory.v
+++ b/rtl/mips_cpu_memory.v
@@ -15,8 +15,8 @@ module mips_cpu_memory(
 );
     parameter RAM_INIT_FILE = "";
     parameter MEM_INIT_FILE = "";
-    reg [31:0] data_memory [0:63];
-    reg [31:0] instr_memory [0:63];
+    reg [31:0] data_memory [0:31];
+    reg [31:0] instr_memory [0:31];
 
     initial begin
         integer i;
@@ -58,11 +58,17 @@ module mips_cpu_memory(
     always_ff @(posedge clk) begin
         $display("Instruction Read: %h", instr_readdata);
         //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
-        if (!data_read & data_write) begin              //cannot read and write to memory in the same cycle
+        if (data_write) begin              //cannot read and write to memory in the same cycle
             if (instr_address != data_address) begin    //cannot modify the instruction being read
-                data_memory[data_address>>2] <= data_writedata;            
+                data_memory[(data_address-32'h00001000)>>2] <= data_writedata; 
+                $display("Store in memory");     
+                $display(data_writedata);      
+            end
+            for (integer k = 0; k<$size(data_memory); k++) begin
+            $display("byte +%h: %h", 32'h00001000+k*4, data_memory[k]);
             end
         end
+        
     end
 endmodule
 
diff --git a/rtl/mips_cpu_pc.v b/rtl/mips_cpu_pc.v
index e0ff344..ba2fc68 100644
--- a/rtl/mips_cpu_pc.v
+++ b/rtl/mips_cpu_pc.v
@@ -23,6 +23,9 @@ always_ff @(posedge clk) begin
 		active <= 1;
 		pc_out <= 32'hBFC00000;
 	end else begin
+		if(pc_out == 32'd0) begin
+			active <= 0;
+		end
 		pc_out <= pc_next;
 		case(pc_ctrl)
 			default: begin
@@ -33,15 +36,18 @@ always_ff @(posedge clk) begin
 			end
 			2'd2: begin // Jump
 				pc_next <= {pc_lit_next[31:28], instr[25:0], 2'b00};
+				$display("Im JUMPING");
+				$display("pc_lit_next: %h", pc_lit_next[31:28]);
+				$display("instr: %b", instr[25:0]);
+				$display("%h",pc_next);
 			end
 			2'd3: begin // Jump using Register
 				pc_next <= reg_readdata;
+				$display("Im JUMPING AROUND LOLOLOL");
+				$display("%h",reg_readdata);
 			end
 		endcase
 	end
-	if (pc_out == 32'd0) begin
-		active <= 0;
-	end
 end
 
 endmodule // pc
\ No newline at end of file
diff --git a/rtl/mips_cpu_regfile.v b/rtl/mips_cpu_regfile.v
index 6ca953f..84d300b 100644
--- a/rtl/mips_cpu_regfile.v
+++ b/rtl/mips_cpu_regfile.v
@@ -29,14 +29,17 @@ always_ff @(negedge clk) begin
 	if (writereg == 5'b00000) begin
 		// skip writing if rd is $0
 	end else if (regwrite) begin
+		$display("%b", opcode);
 		case (opcode)
 			6'b100000: begin //lb, load byte
-				case (readdata1[1:0])
+				case (readdata1[1:0])	
 					2'b00: memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]};
 					2'b01: memory[writereg] <= {{24{writedata[15]}}, writedata[15:8]};
 					2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]};
 					2'b11: memory[writereg] <= {{24{writedata[31]}}, writedata[31:24]};
 				endcase // readdata1[1:0]
+				$display("writedata %h", writedata);
+				$display("memory writereg %h", memory[writereg]);
 			end
 			6'b100100: begin //lbu, load byte unsigned
 				case (readdata1[1:0])
@@ -59,9 +62,6 @@ always_ff @(negedge clk) begin
 				endcase // readdata1[1:0]
 			end
 			6'b100010: begin //lwl, load word left
-				$display("LWLWLWLWLWLWWL");
-				$display(readdata1[1:0]);
-				$display("%h",memory[writereg]);
 				case (readdata1[1:0])
 					2'b00: memory[writereg][31:24] <= writedata[7:0];
 					2'b01: memory[writereg][31:16] <= writedata[15:0];
diff --git a/test/test_mips_cpu_custom.sh b/test/test_mips_cpu_custom.sh
index 24d006e..eac765d 100644
--- a/test/test_mips_cpu_custom.sh
+++ b/test/test_mips_cpu_custom.sh
@@ -1,15 +1,15 @@
 #!/bin/bash
-#:'
+
 # arithmetic
 bash test/test_mips_cpu_harvard.sh rtl addu             #Pass
 bash test/test_mips_cpu_harvard.sh rtl addiu            #Pass
-bash test/test_mips_cpu_harvard.sh rtl ori              #Pass
+bash test/test_mips_cpu_harvard.sh rtl subu             #Pass
 bash test/test_mips_cpu_harvard.sh rtl and              #Pass
 bash test/test_mips_cpu_harvard.sh rtl andi             #Pass
 bash test/test_mips_cpu_harvard.sh rtl or               #Pass
+bash test/test_mips_cpu_harvard.sh rtl ori              #Pass
 bash test/test_mips_cpu_harvard.sh rtl xor              #Pass
 bash test/test_mips_cpu_harvard.sh rtl xori             #Pass
-bash test/test_mips_cpu_harvard.sh rtl subu             #Pass
 #bash test/test_mips_cpu_harvard.sh rtl div
 #bash test/test_mips_cpu_harvard.sh rtl divu
 #bash test/test_mips_cpu_harvard.sh rtl mthi
@@ -29,38 +29,39 @@ bash test/test_mips_cpu_harvard.sh rtl bltzal           #Pass
 bash test/test_mips_cpu_harvard.sh rtl bne              #Pass
 
 # jumps
-#bash test/test_mips_cpu_harvard.sh rtl j
-#bash test/test_mips_cpu_harvard.sh rtl jalr
-#bash test/test_mips_cpu_harvard.sh rtl jal
-#bash test/test_mips_cpu_harvard.sh rtl jr
+#bash test/test_mips_cpu_harvard.sh rtl j               #Need new testcase
+#bash test/test_mips_cpu_harvard.sh rtl jalr            #Again how to link?
+#bash test/test_mips_cpu_harvard.sh rtl jal             #how to link?
+bash test/test_mips_cpu_harvard.sh rtl jr               #Pass
 
 # shift
 bash test/test_mips_cpu_harvard.sh rtl sll              #Pass
 bash test/test_mips_cpu_harvard.sh rtl srl              #Pass
-#bash test/test_mips_cpu_harvard.sh rtl sra
-#bash test/test_mips_cpu_harvard.sh rtl srav
-#bash test/test_mips_cpu_harvard.sh rtl srlv
-#'
+bash test/test_mips_cpu_harvard.sh rtl sra              #Pass
+bash test/test_mips_cpu_harvard.sh rtl srav             #Pass
+bash test/test_mips_cpu_harvard.sh rtl sllv             #Pass
+bash test/test_mips_cpu_harvard.sh rtl srlv             #Pass
+
 
 
 # load & store
 bash test/test_mips_cpu_harvard.sh rtl lw               #Pass
-bash test/test_mips_cpu_harvard.sh rtl lb
-bash test/test_mips_cpu_harvard.sh rtl lbu
-bash test/test_mips_cpu_harvard.sh rtl lh
-bash test/test_mips_cpu_harvard.sh rtl lhu
-bash test/test_mips_cpu_harvard.sh rtl lui
-bash test/test_mips_cpu_harvard.sh rtl lwl
-bash test/test_mips_cpu_harvard.sh rtl lwr
-#bash test/test_mips_cpu_harvard.sh rtl sw
-#bash test/test_mips_cpu_harvard.sh rtl sb
-#bash test/test_mips_cpu_harvard.sh rtl sh
+bash test/test_mips_cpu_harvard.sh rtl lb               #Pass
+bash test/test_mips_cpu_harvard.sh rtl lbu              #Pass
+bash test/test_mips_cpu_harvard.sh rtl lh               #Pass
+bash test/test_mips_cpu_harvard.sh rtl lhu              #Pass
+bash test/test_mips_cpu_harvard.sh rtl lui              #Pass
+bash test/test_mips_cpu_harvard.sh rtl lwl              #Pass
+bash test/test_mips_cpu_harvard.sh rtl lwr              #Pass
+bash test/test_mips_cpu_harvard.sh rtl sw               #Pass
+#bash test/test_mips_cpu_harvard.sh rtl sb              #Once switched to bus
+#bash test/test_mips_cpu_harvard.sh rtl sh              #Once switched to bus
 
 
-# set on less than
-#bash test/test_mips_cpu_harvard.sh rtl slti
-#bash test/test_mips_cpu_harvard.sh rtl sltiu           
-#bash test/test_mips_cpu_harvard.sh rtl slt             # missing
-#bash test/test_mips_cpu_harvard.sh rtl sltu             #Pass
+# set on less than **Branch delay slots dont work on these...
+bash test/test_mips_cpu_harvard.sh rtl slti             #Pass
+bash test/test_mips_cpu_harvard.sh rtl sltiu            #Pass
+bash test/test_mips_cpu_harvard.sh rtl slt              #Pass
+bash test/test_mips_cpu_harvard.sh rtl sltu             #Pass
 
 
diff --git a/test/test_mips_cpu_harvard.sh b/test/test_mips_cpu_harvard.sh
index 0e2b094..880488a 100644
--- a/test/test_mips_cpu_harvard.sh
+++ b/test/test_mips_cpu_harvard.sh
@@ -53,7 +53,7 @@ iverilog -Wall -g2012 \
     -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
     -P mips_cpu_harvard_tb.MEM_INIT_FILE=\"inputs/${INSTR}.data.txt\" \
     -o exec/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
-    ${SRC} 2> /dev/null
+    ${SRC} #2> /dev/null
 /mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${INSTR} &> ./inputs/${INSTR}.log.txt;            # log file for debugging (contains $display)
 echo "$(tail -1 ./inputs/${INSTR}.log.txt)" > ./inputs/${INSTR}.out.txt;                                            # register v0 output to compare with reference
 if diff -w ./inputs/${INSTR}.out.txt ./inputs/${INSTR}.ref.txt &> /dev/null                                         # compare
diff --git a/testbench/mips_cpu_harvard_tb.v b/testbench/mips_cpu_harvard_tb.v
index 70b7a44..b512ce0 100644
--- a/testbench/mips_cpu_harvard_tb.v
+++ b/testbench/mips_cpu_harvard_tb.v
@@ -69,7 +69,11 @@ module mips_cpu_harvard_tb;
             //$display("Clk: %d", clk);
             @(posedge clk);
             //$display("Register v0: %d", register_v0);
-            $display("Reg File Write data: %d", cpuInst.in_writedata);
+            //$display("Reg File Write data: %d", cpuInst.in_writedata);
+            $display("Reg File Out Read data: %h", cpuInst.out_readdata1);
+            $display("Reg File opcode: %b", cpuInst.regfile.opcode);
+            //$display("ALU output: %h", cpuInst.out_ALURes);
+            //$display("ALU input B: %h", cpuInst.alu.B);
         end
         @(posedge clk);
         $display("TB: CPU Halt; active=0");