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Updated ALU and Control
This commit is contained in:
jc4419
parent
a2bcf3ed1b
commit
9198c4f51b
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@ -1,6 +1,6 @@
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module mips_cpu_alu(
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input signed logic[31:0] A, //Bus A - Input from the Readdata1 output from the reg file which corresponds to rs.
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input signed logic[31:0] B, //Bus B - Input from the Readdata2 output from the reg file which corresponds to rt.
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input logic[31:0] A, //Bus A - Input from the Readdata1 output from the reg file which corresponds to rs.
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input logic[31:0] B, //Bus B - Input from the Readdata2 output from the reg file which corresponds to rt. Or from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0].
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input logic [4:0] ALUOp, // 5-bit output from Control that tells the alu what operation to do from a list of 20 distinct alu operations(see below).
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input logic [4:0] shamt, //5-bit input used to specify shift amount for shift operations. Taken directly from the R-type instruction (Non-Variable) or from
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@ -11,9 +11,9 @@ module mips_cpu_alu(
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/*
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Alu Operations:
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-Manipulation Operations: The perform an operation on a value(s).
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- Addition
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- Subtraction
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-Manipulation Operations: They perform an operation on a value(s) and have an output to ALURes.
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- Addition (unsigned)
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- Subtraction (unsigned)
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- Multiplication
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- Division
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- Bitwise AND
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@ -25,14 +25,18 @@ Alu Operations:
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- Shift Right Logical Variable
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- Shift Right Arithmetic
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- Shift Right Arithmetic Variable
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-Condtional Check Operations: They check conditions.
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- Equality (=)
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- Less Than (<)
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- Less Than or Equal To (<=)
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- Greater Than (>)
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- Greater Than or Equal to (>=)
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- Negative Equality(=/=)
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-Implementation Operation:
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- Set On Less Than (signed)
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- Set On Less Than Unsigned
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- Multiplication (unsigned)
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- Division (unsigned)
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-Condtional Check Operations: They check conditions and have an output to ALUCond
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- Equality (=) (signed)
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- Less Than (<) (signed)
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- Less Than or Equal To (<=) (signed)
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- Greater Than (>) (signed)
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- Greater Than or Equal to (>=) (signed)
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- Negative Equality(=/=) (signed)
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-Implementation Operation: A design choice used for implmentation.
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- Pass-through (Used to implement MTHI and MTLO, as these instructions do not need the ALU but the alu is in the pathway to the regfile, so the register value simply passes through.)
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*/
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@ -41,8 +45,8 @@ Alu Operations:
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ADD = 5'd0,
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SUB = 5'd1,
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MUL = 5'd2,
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DIV = 5'd3,
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MUL = 5'd2,//signed multiply
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DIV = 5'd3,//signed divide
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AND = 5'd4,
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OR = 5'd5,
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XOR = 5'd6,
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@ -58,11 +62,16 @@ Alu Operations:
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GRT = 5'd16,
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GEQ = 5'd17,
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NEQ = 5'd18,
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PAS = 5'd19
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PAS = 5'd19,
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SLT = 5'd20,//signed compare
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SLTU = 5'd21,//unsigned compare
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MULU = 5'd22,//unsigned divide
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DIVU = 5'd23//unsigned multiply
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} Ops;
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Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming errors, as a result of enum implemetnation quirks.
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Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming errors, as a result of enum implemetnation.
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assign ALUOps = ALUOp
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@ -72,19 +81,19 @@ assign ALUOps = ALUOp
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case(ALUOps)
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ADD: begin
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ALURes = A + B;
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ALURes = $signed(A) + $signed(B);
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end
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SUB: begin
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ALURes = A - B;
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ALURes = $signed(A) - $signed(B) ;
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end
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MUL: begin
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ALURes = A * B;
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ALURes = $signed(A) * $signed(B);
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end
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DIV: begin
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ALURes = A / B;
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ALURes = $signed(A) / $signed(B);
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end
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AND: begin
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@ -124,7 +133,7 @@ assign ALUOps = ALUOp
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end
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EQ: begin
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if A == B begin
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if ($signed(A) == $signed(B)) begin
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ALUCond = 1;
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end
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else begin
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@ -134,7 +143,7 @@ assign ALUOps = ALUOp
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end
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LES: begin
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if A < B begin
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if ($signed(A) < $signed(B)) begin
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ALUCond = 1;
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end
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else begin
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@ -144,17 +153,7 @@ assign ALUOps = ALUOp
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end
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LEQ: begin
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if A <= B begin
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ALUCond = 1;
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end
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else begin
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ALUCond = 0;
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end
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end
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LEQ: begin
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if A <= B begin
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if ($signed(A) <= $signed(B)) begin
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ALUCond = 1;
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end
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else begin
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@ -164,7 +163,7 @@ assign ALUOps = ALUOp
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end
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GRT: begin
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if A > B begin
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if ($signed(A) > $signed(B)) begin
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ALUCond = 1;
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end
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else begin
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@ -174,7 +173,7 @@ assign ALUOps = ALUOp
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end
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GEQ: begin
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if A >= B begin
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if ($signed(A) >= $signed(B)) begin
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ALUCond = 1;
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end
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else begin
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@ -184,7 +183,7 @@ assign ALUOps = ALUOp
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end
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NEQ: begin
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if A != B begin
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if ($signed(A) != $signed(B)) begin
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ALUCond = 1;
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end
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else begin
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@ -197,6 +196,26 @@ assign ALUOps = ALUOp
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ALURes = A;
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end
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SLT: begin
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if ($signed(A) < $signed(B)) begin
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ALURes = 1;
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end
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end
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SLTU: begin
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if (A < B) begin
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ALURes = 1;
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end
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end
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MULU: begin
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ALURes = A * B;
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end
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DIVU: begin
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ALURes = A / B;
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end
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endcase
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end
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endmodule
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@ -1,319 +1,201 @@
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/*
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Instr
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*0: XOR SUBU SRLV SRL SRAV SRA SLTU SLT SLLV
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SLL OR MULTU MULT MTLO MTHI JR JALR DIVU
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DIV AND ADDU
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1: BLTZAL BLTZ BGEZAL BGEZ
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2: J
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3: JAL
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4: BEQ
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5: BNE
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6: BLEZ
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7: BGTZ
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*9: ADDIU
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10: SLTI
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11: SLTIU
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12: ANDI
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13: ORI
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14: XORI
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15: LUI
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32: LB
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33: LH
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34: LWL
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*35: LW
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36: LBU
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37: LHU
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38: LWR
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40: SB
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41: SH
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*43: SW
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*/
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module mips_cpu_control(
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/*
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Regdst:
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00:Instr[20-16]
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01:Instr[15-11]
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10:2'd31
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*/
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input logic[31:0] Instr,
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input logic ALUCond,
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/*
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Memtoreg:
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00: Alu output
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01: Memory output
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10: PC+4 output
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*/
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output logic CtrlRegDst,
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output logic[1:0] CtrlPC,
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output logic CtrlMemRead,
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output logic CtrlMemtoReg,
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output logic[4:0] CtrlALUOp,
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output logic[4:0] Ctrlshamt,
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output logic CtrlMemWrite,
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output logic CtrlALUSrc,
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output logic CtrlRegWrite
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//Commented signals represents dont care(x)
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module mips_cpu_control{
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input logic[5:0] Instr,
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input logic[5:0] rt,
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output logic[1:0] Regdst,
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output logic Branch,
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output logic Memread,
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output logic[1:0] Memtoreg,
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output logic Memwrite,
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output logic Alusrc,
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output logic Regwrite,
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output logic Jump,
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);
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/* logic[5:0] op;
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logic[5:0] funct;
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logic[4:0] rt; */
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/* assign op = Instr[31:26];
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assign funct = Instr[5:0];
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assign rt = Instr[20:16]; */
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typedef enum logic[5:0]{
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SPECIAL = 6'd0,
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REGIMM = 6'd1,
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J = 6'd2,
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JAL = 6'd3,
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BEQ = 6'd4,
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BNE = 6'd5,
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BLEZ = 6'd6,
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BGTZ = 6'd7,
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ADDI = 6'd8,
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ADDIU = 6'd9,
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SLTI = 6'd10,
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SLTIU = 6'd11,
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ANDI = 6'd12,
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ORI = 6'd13,
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XORI = 6'd14,
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LUI = 6'd15,
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LB = 6'd32,
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LH = 6'd33,
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LWL = 6'd34,
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LW = 6'd35,
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LBU = 6'd36,
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LHU = 6'd37,
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LWR = 6'd38,
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SB = 6'd40,
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SH = 6'd41,
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SW = 6'd43
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} op_enum;
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op_enum op;
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assign op = Instr[31:26];
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typedef enum logic[5:0]{
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SLL = 6'd0,
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SRL = 6'd2,
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SRA = 6'd3,
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SLLV = 6'd4,
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SRLV = 6'd6,
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SRAV = 6'd7,
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JR = 6'd8,
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JALR = 6'd9,
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MTHI = 6'd17,
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MTLO = 6'd19,
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MULT = 6'd24,
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MULTU = 6'd25,
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DIV = 6'd26,
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DIVU = 6'd27,
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ADDU = 6'd33,
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SUBU = 6'd35,
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AND = 6'd36,
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OR = 6'd37,
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XOR = 6'd38,
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SLT = 6'd42,
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SLTU = 6'd43
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} funct_enum;
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funct_enum funct;
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assign funct = Instr[5:0];
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typedef enum logic[4:0]{
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BLTZ = 5'd0,
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BGEZ = 5'd1,
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BLTZAL = 5'd16,
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BGEZAL = 5'd17
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} rt_enum;
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rt_enum rt;
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assign rt = Instr[20:16];
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always_comb begin
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case(Instr)
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6'd0: begin
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Regdst=2'b01;
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Branch=0;
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Memread=0;
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Memwrite=0;
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Memtoreg=2'b00;
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Alusrc=0;
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Regwrite=1;
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Jump=0;
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end
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6'd1: begin
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Regdst=2'b10;
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Branch=1;
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Memread=0;
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Memwrite=0;
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if(rt[5]==1)begin
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Memtoreg=2'b10;
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Regwrite=1;
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end
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Alusrc=0;
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Jump=0;
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end
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6'd2: begin
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//Regdst=2'b;
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Branch=0;
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Memread=0;
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//Memtoreg=;
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Memwrite=0;
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//Alusrc=;
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Regwrite=0;
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Jump=1;
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end
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6'd3: begin
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Regdst=2'b10;
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Branch=0;
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Memread=0;
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Memtoreg=2'b10;
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Memwrite=0;
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//Alusrc=;
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Regwrite=1;
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Jump=1;
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end
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6'd4: begin
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//Regdst=2'b;
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0;
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Jump=0;
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end
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6'd5: begin
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//Regdst=2'b;
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0
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Jump=0;
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end
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6'd6: begin
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//Regdst=2'b;
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0;
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Jump=0;
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end
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6'd7: begin
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//Regdst=2'b;
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0;
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Jump=0;
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end
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6'd9: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd10: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd11: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd12: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd13: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd14: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd15: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2b'00;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd32: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd33: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd34: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd35: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Memwrite=0;
|
||||
Alusrc=1;
|
||||
Regwrite=1;
|
||||
Jump=0;
|
||||
end
|
||||
6'd36: begin
|
||||
Regdst=2'b00;
|
||||
Branch=0;
|
||||
Memread=1;
|
||||
Memtoreg=2'b01;
|
||||
Memwrite=0;
|
||||
Alusrc=1;
|
||||
Regwrite=1;
|
||||
Jump=0;
|
||||
end
|
||||
6'd37: begin
|
||||
Regdst=2'b00;
|
||||
Branch=0;
|
||||
Memread=1;
|
||||
Memtoreg=2'b01;
|
||||
Memwrite=0;
|
||||
Alusrc=1;
|
||||
Regwrite=1;
|
||||
Jump=0;
|
||||
end
|
||||
6'd38: begin
|
||||
Regdst=2'b00;
|
||||
Branch=0;
|
||||
Memread=1;
|
||||
Memtoreg=2'b01;
|
||||
Memwrite=0;
|
||||
Alusrc=1;
|
||||
Regwrite=1;
|
||||
Jump=0;
|
||||
end
|
||||
6'd40: begin
|
||||
//Regdst=2'b;
|
||||
Branch=0;
|
||||
Memread=0;
|
||||
//Memtoreg=;
|
||||
Memwrite=1;
|
||||
Alusrc=1;
|
||||
Regwrite=0;
|
||||
Jump=0;
|
||||
end
|
||||
6'd41: begin
|
||||
//Regdst=2'b;
|
||||
Branch=0;
|
||||
Memread=0;
|
||||
//Memtoreg=;
|
||||
Memwrite=1;
|
||||
Alusrc=1;
|
||||
Regwrite=0;
|
||||
Jump=0;
|
||||
end
|
||||
6'd43: begin
|
||||
//Regdst=2'b;
|
||||
Branch=0;
|
||||
Memread=0;
|
||||
//Memtoreg=;
|
||||
Memwrite=1;
|
||||
Alusrc=1;
|
||||
Regwrite=0;
|
||||
Jump=0;
|
||||
end
|
||||
endcase
|
||||
|
||||
//CtrlRegDst logic
|
||||
if(op == (ADDIU | ANDI | LB | LBU | LH | LHU | LUI | LW | LWL | LWR | ORI | SLTI | SLTIU | XORI))begin
|
||||
CtrlRegDst = 0; //Write address comes from rt
|
||||
end else if (op == (SPECIAL & (funct == (ADDU | AND | JALR | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR))))begin
|
||||
CtrlRegDst = 1; //Write address comes from rd
|
||||
end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes
|
||||
|
||||
//CtrlPC logic
|
||||
if(op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL)))))begin
|
||||
CtrlPC = 2'd1; // Branches - Jumps relative to PC
|
||||
end else if(op == (J | JAL))begin
|
||||
CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
|
||||
end else if(op == (JR | JALR))begin
|
||||
CtrlPC = 2'd3; // Jumps using Register.
|
||||
end else begin CtrlPC = 2'd0;end // No jumps, just increment to next word
|
||||
|
||||
//CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
|
||||
if(op == (LB | LBU | LH | LHU | LW | LWL | LWR))begin
|
||||
CtrlMemRead = 1;//Memory is read enabled
|
||||
CtrlMemtoReg = 1;//write data port of memory is fed from data memory
|
||||
end else if (op == (ADDIU | ANDI | ORI | SLTI | SLTIU | XORI | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MTHI | MTLO | MULT | MULTU | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin
|
||||
CtrlMemRead = 0;//Memory is read disabled
|
||||
CtrlMemtoReg = 0;//write data port of memory if fed from ALURes
|
||||
end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
|
||||
|
||||
//CtrlALUOp Logic
|
||||
if(op == (ADDIU | (SPECIAL & (funct == ADDU))))begin
|
||||
CtrlALUOp = 5'd0; //ADD from ALUOps
|
||||
end else if (op == (ANDI | (SPECIAL & (funct == AND))))begin
|
||||
CtrlALUOp = 5'd4;//AND from ALUOps
|
||||
end else if (op == BEQ) begin
|
||||
CtrlALUOp = 5'd13;//EQ from ALUOps
|
||||
end else if (op == (REGIMM & (rt == (BGEZ | BGEZAL))))begin
|
||||
CtrlALUOp = 5'd17;//GEQ from ALUOps
|
||||
end else if (op == BGTZ)begin
|
||||
CtrlALUOp = 5'd16;//GRT from ALUOps
|
||||
end else if (op == BLEZ)begin
|
||||
CtrlALUOp = 5'd15;//LEQ from ALUOps
|
||||
end else if (op == (REGIMM & (rt == (BLTZ | BLTZAL))))begin
|
||||
CtrlALUOp = 5'd14;//LES from ALUOps
|
||||
end else if (OP == BNE)begin
|
||||
CtrlALUOp = 5'd18;//NEQ from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == DIV)))begin
|
||||
CtrlALUOp = 5'd3;//DIV from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == DIVU)))begin
|
||||
CtrlALUOp = 5'd23;//DIVU from ALUOps
|
||||
end else if (op == (LB | LBU | LH | LHU | LW | LWL | LWR | SB | SBH | SW))begin
|
||||
CtrlALUOp = 5'd0;//ADD from ALUOps
|
||||
end else if (op == LUI)begin
|
||||
CtrlALUOp = 5'd7;//SLL from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == MTHI | MTLO)))begin
|
||||
CtrlALUOp = 5'd19;//PAS from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == MULT)))begin
|
||||
CtrlALUOp = 5'd2;//MUL from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == MULTU)))begin
|
||||
CtrlALUOp = 5'd22;//MULU from ALUOps
|
||||
end else if (op == (ORI | (SPECIAL & (funct == OR))))begin
|
||||
CtrlALUOp = 5'd5;//OR from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == SLL)))begin
|
||||
CtrlALUOp = 5'd7;//SLL from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == SLLV)))begin
|
||||
CtrlALUOp = 5'd8;//SLLV from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == SRA)))begin
|
||||
CtrlALUOp = 5'd11;//SRA from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == SRAV)))begin
|
||||
CtrlALUOp = 5'd12;//SRAV from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == SRL)))begin
|
||||
CtrlALUOp = 5'd9;//SRL from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == SRLV)))begin
|
||||
CtrlALUOp = 5'd10;//SRLV from ALUOps
|
||||
end else if (op == (SLTI | (SPECIAL & (funct == SLT))))begin
|
||||
CtrlALUOp = 5'd20;//SLT from ALUOps
|
||||
end else if (op == (SLTIU | (SPECIAL & (funct == SLTU))))begin
|
||||
CtrlALUOp = 5'd21;//SLTU from ALUOps
|
||||
end else if (op == (SPECIAL & (funct == SUBU)))begin
|
||||
CtrlALUOp = 5'd1;//SUB from ALUOps
|
||||
end else if (op == (XORI | (SPECIAL & (funct == XOR))))begin
|
||||
CtrlALUOp = 5'd6;//XOR from ALUOps
|
||||
end else begin
|
||||
CtrlALUOp = 5'bxxxxx;
|
||||
end
|
||||
|
||||
//Ctrlshamt logic
|
||||
if(op == (SPECIAL & (funct == (SRA | SRL | SLL))))begin
|
||||
Ctrlshamt = Instr[10:6];// Shift amount piped in from the instruction
|
||||
end else if(op == LUI)begin
|
||||
Ctrlshamt = 5'd16;//Used specifically to implement LUI as the instruction itslef does not include shamt
|
||||
end else begin Ctrlshamt = 5'bxxxxx;end
|
||||
|
||||
//CtrlMemWrite logic
|
||||
if(op == (SB | SH | SW)begin
|
||||
CtrlMemWrite = 1;//Memory is write enabled
|
||||
end else begin CtrlMemWrite = 0;end//default is 0 to ensure no accidental overwriting.
|
||||
|
||||
//CtrlALUSrc logic
|
||||
if(op == (ADDIU | ANDI | LUI | ORI | SLTI | SLTIU | XORI | LB | LBU | LH | LHU | LW | LWL | LWR | SB | SH | SW)begin
|
||||
CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0]
|
||||
end else if (op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL)) (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | OR | SLLV | SLT | SLTU | SRAV | SRLV | SUBU | XOR)))))begin
|
||||
CtrlALUSrc = 0;///ALU Bus B is fed from rt.
|
||||
end else begin CtrlALUSrc = 1'bx;end
|
||||
|
||||
//CtrlRegWrite logic
|
||||
if(op == (ADDIU | ANDI | LB | LBU | LH | LHU | LUI | LW | LWL | LWR | ORI | SLTI | SLTIU | XORI | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | JALR | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin
|
||||
CtrlRegWrite = 1;//The Registers are Write Enabled
|
||||
end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in a new issue