From 8f5e582f33bd85496b723a40841931a851c34a11 Mon Sep 17 00:00:00 2001
From: jc4419 <60656643+jc4419@users.noreply.github.com>
Date: Mon, 7 Dec 2020 18:18:19 +0400
Subject: [PATCH] Updated ALU - Minor Syntax Fixes

---
 rtl/mips_cpu_control.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v
index 0bac657..c61dfe8 100644
--- a/rtl/mips_cpu_control.v
+++ b/rtl/mips_cpu_control.v
@@ -181,14 +181,14 @@ always_comb begin
     end else begin Ctrlshamt = 5'bxxxxx;end
 
     //CtrlMemWrite logic
-    if(op == (SB | SH | SW)begin
+    if(op == (SB | SH | SW))begin
         CtrlMemWrite = 1;//Memory is write enabled
     end else begin CtrlMemWrite = 0;end//default is 0 to ensure no accidental overwriting.
     
     //CtrlALUSrc logic
-    if(op == (ADDIU | ANDI | LUI | ORI | SLTI | SLTIU | XORI | LB | LBU | LH | LHU | LW | LWL | LWR | SB | SH | SW)begin
+    if(op == (ADDIU | ANDI | LUI | ORI | SLTI | SLTIU | XORI | LB | LBU | LH | LHU | LW | LWL | LWR | SB | SH | SW))begin
         CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0]
-    end else if (op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL)) (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | OR | SLLV | SLT | SLTU | SRAV | SRLV | SUBU | XOR)))))begin 
+    end else if (op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL))) | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | OR | SLLV | SLT | SLTU | SRAV | SRLV | SUBU | XOR)))))begin 
         CtrlALUSrc = 0;///ALU Bus B is fed from rt.
     end else begin CtrlALUSrc = 1'bx;end