From 8d100e8693b83252fc2eda43608e4752b2db102a Mon Sep 17 00:00:00 2001 From: jl7719 Date: Sat, 19 Dec 2020 10:55:41 +0000 Subject: [PATCH] Update regfile and harvard to enable register reset --- rtl/mips_cpu_harvard.v | 1 + rtl/mips_cpu_regfile.v | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/rtl/mips_cpu_harvard.v b/rtl/mips_cpu_harvard.v index ecf4088..39fc962 100644 --- a/rtl/mips_cpu_harvard.v +++ b/rtl/mips_cpu_harvard.v @@ -117,6 +117,7 @@ mips_cpu_control control( //instance of the 'mips_cpu_control' module called 'co mips_cpu_regfile regfile( //Inputs to refile .clk(clk), //clock input for triggering write port + .rst(reset), .readreg1(in_readreg1), //read port 1 selector .readreg2(in_readreg2), //read port 2 selector .writereg(in_writereg), //write port selector diff --git a/rtl/mips_cpu_regfile.v b/rtl/mips_cpu_regfile.v index cad3794..b789a81 100644 --- a/rtl/mips_cpu_regfile.v +++ b/rtl/mips_cpu_regfile.v @@ -1,5 +1,6 @@ module mips_cpu_regfile( input logic clk, //clock input for triggering write port +input logic rst, input logic[4:0] readreg1, //read port 1 register selector input logic[4:0] readreg2, //read port 2 register selector input logic[4:0] writereg, //write port register selector @@ -26,6 +27,13 @@ assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory assign readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector assign readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector +always_ff @(posedge rst) begin + integer i; //Initialise to zero when reset + for (i = 0; i < 32; i++) begin + memory[i] = 0; + end +end + always_ff @(negedge clk) begin if (writereg == 5'b00000) begin // skip writing if rd is $0