From 3433337eba97443b5da953f7b3e2186aca069a38 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Tue, 1 Dec 2020 23:04:43 +0000 Subject: [PATCH 1/3] Added Regfile Missing partial/misaligned loads --- rtl/mips_cpu_harvard.v | 1 + rtl/mips_cpu_regfile.v | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 rtl/mips_cpu_regfile.v diff --git a/rtl/mips_cpu_harvard.v b/rtl/mips_cpu_harvard.v index 5997c0c..169361e 100644 --- a/rtl/mips_cpu_harvard.v +++ b/rtl/mips_cpu_harvard.v @@ -75,6 +75,7 @@ control control( //control flags block ); regfile regfile( +.clk(clk), //clock input for triggering write port .readreg1(rs), .readreg2(rt), .writereg(rd), diff --git a/rtl/mips_cpu_regfile.v b/rtl/mips_cpu_regfile.v new file mode 100644 index 0000000..8d69b64 --- /dev/null +++ b/rtl/mips_cpu_regfile.v @@ -0,0 +1,35 @@ +module regfile( +input logic clk, //clock input for triggering write port +input logic[4:0] readreg1, //read port 1 selector +input logic[4:0] readreg2, //read port 2 selector +input logic[4:0] writereg, //write port selector +input logic[31:0] writedata, //write port input data +input logic regwrite, //enable line for write port +output logic[31:0] readdata1, //read port 1 output +output logic[31:0] readdata2, //read port 2 output +output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results) +); + +reg[31:0] memory [31:0]; //32 register slots, 32-bits wide + +initial begin + integer i; //Initialise to zero by default + for (i = 0; i < 31; i++) begin + memory[i] = 0; + end +end + +assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory + +always_comb begin + readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector + readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector +end + +always_ff @(posedge clk) begin + if (regwrite) begin + memory[writereg] <= writedata; + end +end + +endmodule : regfile \ No newline at end of file From 27cccc28b8ecf6d8ef171b0248b10c4917abb213 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 2 Dec 2020 01:04:57 +0000 Subject: [PATCH 2/3] Added partial loads to regfile Partial reads are handled within the ALU --- rtl/mips_cpu_harvard.v | 15 ++++++++------- rtl/mips_cpu_regfile.v | 33 ++++++++++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/rtl/mips_cpu_harvard.v b/rtl/mips_cpu_harvard.v index 169361e..ba36e1e 100644 --- a/rtl/mips_cpu_harvard.v +++ b/rtl/mips_cpu_harvard.v @@ -76,13 +76,14 @@ control control( //control flags block regfile regfile( .clk(clk), //clock input for triggering write port -.readreg1(rs), -.readreg2(rt), -.writereg(rd), -.writedata(writeback), -.regwrite(RegWrite), -.readdata1(read_data1), -.readdata2(read_data2), +.readreg1(rs), //read port 1 selector +.readreg2(rt), //read port 2 selector +.writereg(rd), //write port selector +.writedata(writeback), //write port input data +.regwrite(RegWrite), //enable line for write port +.opcode(opcode), //opcode input for controlling partial load weirdness +.readdata1(read_data1), //read port 1 output +.readdata2(read_data2), //read port 2 output .regv0(register_v0) //debug output of $v0 or $2 (first register for returning function results ); diff --git a/rtl/mips_cpu_regfile.v b/rtl/mips_cpu_regfile.v index 8d69b64..71a3007 100644 --- a/rtl/mips_cpu_regfile.v +++ b/rtl/mips_cpu_regfile.v @@ -5,6 +5,7 @@ input logic[4:0] readreg2, //read port 2 selector input logic[4:0] writereg, //write port selector input logic[31:0] writedata, //write port input data input logic regwrite, //enable line for write port +input[5:0] opcode, //opcode input for controlling partial load weirdness output logic[31:0] readdata1, //read port 1 output output logic[31:0] readdata2, //read port 2 output output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results) @@ -28,7 +29,37 @@ end always_ff @(posedge clk) begin if (regwrite) begin - memory[writereg] <= writedata; + case (opcode) + 6'b100000: begin //lb, load byte + memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]}; + end + 6'b100100: begin //lbu, load byte unsigned + memory[writereg] <= {{24{1'b0}}, writedata[7:0]}; + end + 6'b100001: begin //lh, load half-word + memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]}; + end + 6'b100101: begin //lhu, load half-word unsigned + memory[writereg] <= {{16{1'b0}}, writedata[15:0]}; + end + 6'b100010: begin //lwl, load word left + case (readdata1[1:0]) + 2'b00: memory[writereg][31:24] <= writedata[7:0]; + 2'b01: memory[writereg][31:16] <= writedata[15:0]; + 2'b10: memory[writereg][31:8] <= writedata[23:0]; + 2'b11: memory[writereg][31:0] <= writedata[31:0]; + endcase // readdata1[1:0] + end + 6'b100110: begin //lwr, load word right + case (readdata1[1:0]) + 2'b00: memory[writereg][31:0] <= writedata[31:0]; + 2'b01: memory[writereg][23:0] <= writedata[31:8]; + 2'b10: memory[writereg][15:0] <= writedata[31:16]; + 2'b11: memory[writereg][7:0] <= writedata[31:24]; + endcase // readdata1[1:0] + end + default: memory[writereg] <= writedata; //most instructions + endcase // opcode end end From 63b017d552cacc01f037b506cf3afc9a1bc1a297 Mon Sep 17 00:00:00 2001 From: yhp19 Date: Wed, 2 Dec 2020 15:43:30 +0800 Subject: [PATCH 3/3] added control comments --- rtl/mips_cpu_control.v | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v index 2927e40..f5a7656 100644 --- a/rtl/mips_cpu_control.v +++ b/rtl/mips_cpu_control.v @@ -46,18 +46,31 @@ Memtoreg: /* Aluop: 0: r-type instructions -1: <0 +1: <0 + -BLTZAL BLTZ 2: >=0 + -BGEZAL BGEZ 3: =0 + -BEQ 4: =/=0 + -BNE 5: <=0 + -BLEZ 6: >0 + -BGTZ 7: add + -ADDIU + -all load and store instructions 8: slt (signed) + -STLI 9: slt (unsigned) + -STLIU 10: and + -ANDI 11: or + -ORI 12: xor + -XORI */ //Commented signals represents dont care(x)