diff --git a/rtl/mips_cpu_memory.v b/rtl/mips_cpu_memory.v
index 05e3e46..66daf1c 100644
--- a/rtl/mips_cpu_memory.v
+++ b/rtl/mips_cpu_memory.v
@@ -56,7 +56,7 @@ module mips_cpu_memory(
 
     //Synchronous write path
     always_ff @(posedge clk) begin
-        $display("Instruction Read: %h", instr_readdata);
+        //$display("Instruction Read: %h", instr_readdata);
         //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
         if (data_write) begin              //cannot read and write to memory in the same cycle
             if (instr_address != data_address) begin    //cannot modify the instruction being read
diff --git a/rtl/mips_cpu_pc.v b/rtl/mips_cpu_pc.v
index 69bd98e..3e1d8e0 100644
--- a/rtl/mips_cpu_pc.v
+++ b/rtl/mips_cpu_pc.v
@@ -26,25 +26,29 @@ always_ff @(posedge clk) begin
 			active <= 0;
 		end
 		pc_out <= pc_next;
+	end
+end
+
+
+always_comb begin
 		case(pc_ctrl)
-			default: begin
-				pc_next <= pc_out + 32'd4;
-			end
 			2'd1: begin // Branch
-				pc_next <= pc_out + 32'd4 + {{14{instr[15]}},instr[15:0],2'b00};
+				pc_next = pc_out + 32'd4 + {{14{instr[15]}},instr[15:0],2'b00};
 			end
 			2'd2: begin // Jump
-				pc_next <= {pc_lit_next[31:28], instr[25:0], 2'b00};
+				pc_next = {pc_lit_next[31:28], instr[25:0], 2'b00};
 				$display("JUMPING");
 				$display("pc_lit_next: %h", pc_lit_next[31:28]);
 				$display("instr: %b", instr[25:0]);
 				$display("%h",pc_next);
 			end
 			2'd3: begin // Jump using Register
-				pc_next <= reg_readdata;
+				pc_next = reg_readdata;
+			end
+			default: begin
+				pc_next = pc_out + 32'd4;
 			end
 		endcase
-	end
 end
 
 endmodule // pc
\ No newline at end of file