From 847bf92add23cddf3b4a3ee41d569c6d95e40bb7 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Wed, 2 Dec 2020 19:13:41 +0000
Subject: [PATCH] Fix regfile hazard from storing when inputs change

---
 rtl/mips_cpu_regfile.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtl/mips_cpu_regfile.v b/rtl/mips_cpu_regfile.v
index 71a3007..c7f8ff0 100644
--- a/rtl/mips_cpu_regfile.v
+++ b/rtl/mips_cpu_regfile.v
@@ -27,7 +27,7 @@ always_comb begin
 	readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector
 end
 
-always_ff @(posedge clk) begin
+always_ff @(negedge clk) begin
 	if (regwrite) begin
 		case (opcode)
 			6'b100000: begin //lb, load byte