Update mips_cpu_memory.v

Change as per constraint
This commit is contained in:
jl7719 2020-11-29 17:44:08 +09:00
parent 7c9fc23f7e
commit 841081c152

View file

@ -5,6 +5,13 @@ Memory for Harvard Interface
- combinatorial read/fetch of instruction via instr_ port
- combinatorial read and single cycle write of data via data_ port
Constraints
read write
0 0 -> nothing
0 1 -> write
1 0 -> read
1 1 -> read ????? probs should never occur?
Instantiation of Memory Module
- mips_cpu_memory #(RAM_INIT_FILE) ramInst(clk, data_address, data_write, data_read, data_writedata, data_readdata, instr_address, instr_readdata);
@ -15,11 +22,12 @@ Special Memory Locations
Needs checking with:
-- clk or clk_enable?
-- constraint on not being able to read and write in the same cycle
-- whether there is a more efficient way of initialising memory to zero (line 32)
*/
module mips_cpu_memory(
input logic clk,
input logic clk_enable,
//Data Memory
input logic[31:0] data_address,
@ -51,14 +59,24 @@ module mips_cpu_memory(
end
//Combinatorial read path for data and instruction.
assign data_readdata = data_read ? memory[data_address] : 16'hxxxx;
assign instr_readdata = memory[instr_address]
if (clk_enable == 1) begin
assign data_readdata = data_read ? memory[data_address] : 16'hxxxx;
assign instr_readdata = memory[instr_address];
end
else begin
assign data_readdata = data_readdata;
assign instr_readdata = instr_address;
end
//Synchronous write path
always_ff @(posedge clk) begin
//$display("RAM : INFO : data_read=%h, data_addr = %h, mem=%h", data_read, data_address, memory[data_address]);
if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
memory[data_address] <= data_writedata;
always_ff @(posedge clk_enable) begin
//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
if (instr_address != data_address) begin //cannot modify the instruction being read
memory[data_address] <= data_writedata;
end
end
end
endmodule