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Update mips_cpu_memory.v
Change as per constraint
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@ -5,6 +5,13 @@ Memory for Harvard Interface
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- combinatorial read/fetch of instruction via instr_ port
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- combinatorial read and single cycle write of data via data_ port
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Constraints
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read write
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0 0 -> nothing
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0 1 -> write
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1 0 -> read
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1 1 -> read ????? probs should never occur?
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Instantiation of Memory Module
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- mips_cpu_memory #(RAM_INIT_FILE) ramInst(clk, data_address, data_write, data_read, data_writedata, data_readdata, instr_address, instr_readdata);
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@ -15,11 +22,12 @@ Special Memory Locations
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Needs checking with:
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-- clk or clk_enable?
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-- constraint on not being able to read and write in the same cycle
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-- whether there is a more efficient way of initialising memory to zero (line 32)
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*/
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module mips_cpu_memory(
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input logic clk,
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input logic clk_enable,
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//Data Memory
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input logic[31:0] data_address,
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@ -51,14 +59,24 @@ module mips_cpu_memory(
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end
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//Combinatorial read path for data and instruction.
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assign data_readdata = data_read ? memory[data_address] : 16'hxxxx;
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assign instr_readdata = memory[instr_address]
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if (clk_enable == 1) begin
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assign data_readdata = data_read ? memory[data_address] : 16'hxxxx;
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assign instr_readdata = memory[instr_address];
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end
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else begin
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assign data_readdata = data_readdata;
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assign instr_readdata = instr_address;
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end
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//Synchronous write path
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always_ff @(posedge clk) begin
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//$display("RAM : INFO : data_read=%h, data_addr = %h, mem=%h", data_read, data_address, memory[data_address]);
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if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
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memory[data_address] <= data_writedata;
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always_ff @(posedge clk_enable) begin
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//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
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if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
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if (instr_address != data_address) begin //cannot modify the instruction being read
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memory[data_address] <= data_writedata;
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end
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end
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end
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endmodule
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