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Add testcases and ref outputs for addiu, and, andi

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jl7719 2020-12-11 15:17:43 +09:00
parent 1bf7b5d40e
commit 7ffd8fb400
7 changed files with 16 additions and 1 deletions
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1
inputs/addiu.ref.txt Normal file
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inputs/addiu.txt Normal file
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3404000a
24820014
00000008

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inputs/and.ref.txt Normal file
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inputs/and.txt Normal file
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3404000A
3405000F
00851024
00000008

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inputs/andi.ref.txt Normal file
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inputs/andi.txt Normal file
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34040005
3082000f
00000008
00000000
00000000

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rtl/mips_cpu_memory.v
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@ -45,7 +45,7 @@ module mips_cpu_memory(
//Synchronous write path //Synchronous write path
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
$display("Instruction Read: %h", instr_readdata); //$display("Instruction Read: %h", instr_readdata);
//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]); //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
if (!data_read & data_write) begin //cannot read and write to memory in the same cycle if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
if (instr_address != data_address) begin //cannot modify the instruction being read if (instr_address != data_address) begin //cannot modify the instruction being read