diff --git a/testbench/mips_cpu_bus_memory.v b/testbench/mips_cpu_bus_memory.v
index a2f47f2..822c423 100644
--- a/testbench/mips_cpu_bus_memory.v
+++ b/testbench/mips_cpu_bus_memory.v
@@ -1,5 +1,6 @@
 module mips_cpu_bus_memory( //Avalon memory mapped bus controller (slave)
     input logic clk,
+    input logic reset,
     input logic[31:0] address,
     input logic write,
     input logic read,
@@ -43,10 +44,20 @@ initial begin
     for (integer i = 0; i<$size(data_memory); i++) begin //Read out data contents to log
         $display("byte +%h: %h", 32'h00001000+i*4, data_memory[i]);
     end
+
+    waitrequest = 1'b0; // set waitrequest low to begin
+    readdata = 32'h00000000; // set readdata low to begin
+
+end
+
+always_comb begin
+    if (reset) begin
+        waitrequest = 1'b0;
+    end
 end
 
 always_ff @(posedge read or posedge write) begin
-    waitrequest <= 1;
+    waitrequest <= 1'b1;
 end
 
 always_ff @(posedge clk) begin
@@ -86,5 +97,4 @@ always_ff @(posedge clk) begin
     end
 end
 
-
 endmodule
\ No newline at end of file
diff --git a/testbench/mips_cpu_bus_tb.v b/testbench/mips_cpu_bus_tb.v
index ee7afa8..bb93aaf 100644
--- a/testbench/mips_cpu_bus_tb.v
+++ b/testbench/mips_cpu_bus_tb.v
@@ -10,6 +10,7 @@ logic[3:0] byteenable;
 
 mips_cpu_bus_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) memInst( //Avalon memory mapped bus controller (slave)
     .clk(clk), // clk input to mem
+    .reset(reset), // reset input to stall mem during cpu reset
     .address(address), // addr input to mem
     .write(write), // write flag input
     .read(read), // read flag input