diff --git a/inputs/addu/addu-2.ref.txt b/inputs/addu/addu-2.ref.txt
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/inputs/addu/addu-2.ref.txt
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/inputs/addu/addu-2.txt b/inputs/addu/addu-2.txt
new file mode 100644
index 0000000..d6bfc13
--- /dev/null
+++ b/inputs/addu/addu-2.txt
@@ -0,0 +1,4 @@
+3C041000
+3C05F000
+00000008
+00851021
diff --git a/inputs/bgezal/bgezal-2.ref.txt b/inputs/bgezal/bgezal-2.ref.txt
new file mode 100644
index 0000000..d8263ee
--- /dev/null
+++ b/inputs/bgezal/bgezal-2.ref.txt
@@ -0,0 +1 @@
+2
\ No newline at end of file
diff --git a/inputs/bgezal/bgezal-2.txt b/inputs/bgezal/bgezal-2.txt
new file mode 100644
index 0000000..dc238df
--- /dev/null
+++ b/inputs/bgezal/bgezal-2.txt
@@ -0,0 +1,5 @@
+3C04FFFF
+04910004
+03E00008
+24420001
+00000008
diff --git a/inputs/jr/jr-3.ref.txt b/inputs/jr/jr-3.ref.txt
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/inputs/jr/jr-3.ref.txt
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/inputs/jr/jr-3.txt b/inputs/jr/jr-3.txt
new file mode 100644
index 0000000..92b32e4
--- /dev/null
+++ b/inputs/jr/jr-3.txt
@@ -0,0 +1,4 @@
+3C05BFC0
+34A50008
+00A00008
+00000008
diff --git a/reference/reference.txt b/reference/reference.txt
index 0639738..8d016c9 100644
--- a/reference/reference.txt
+++ b/reference/reference.txt
@@ -30,6 +30,20 @@ ADDU $2,$4,$5
 
 register_v0 = 8
 
+-Test not overflowing property
+
+lui $4,$0,0x1000
+lui $5,$0,0xF000
+JR $0
+ADDU $2,$4,$5
+
+3C041000
+3C05F000
+00000008
+00851021
+
+register_v0 = 0
+
 ==AND Bitwise and==
 
 LUI $5,0xCCCC
@@ -126,6 +140,22 @@ JR $31
 
 register_v0 = 2
 
+-Testing whether it would link if branch fails
+
+lui $4,0xFFFF
+BGEZAL $4,4
+JR $31
+ADDIU $2,$2,1
+JR $0
+
+3C04FFFF
+04910004
+03E00008
+24420001
+00000008
+
+register_v0 = 2
+
 ==BGTZ Branch on greater than zero==
 
 ORI $4,$0,3
@@ -363,6 +393,20 @@ ORI $2,$0,5
 
 register_v0 = 5
 
+-This broke testbench once due to log.txt weirdness
+
+LUI $5,0xBFC0  
+ORI $5,$5,0x0008
+JR $5  
+JR $0
+
+3C05BFC0
+34A50008
+00A00008
+00000008
+
+register_v0 = 0
+
 ==LB	Load byte==
 
 ORI $4,$0,0x1001