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Update mips_cpu_regfile.v

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Regfile should now compile, write is skipped if $0 is the destination register
This commit is contained in:
Aadi Desai 2020-12-08 13:23:08 +00:00
parent 9de2b59bbb
commit 6becea322f
1 changed files with 4 additions and 3 deletions
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7
rtl/mips_cpu_regfile.v
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@ -15,12 +15,11 @@ reg[31:0] memory [31:0]; //32 register slots, 32-bits wide
initial begin initial begin
integer i; //Initialise to zero by default integer i; //Initialise to zero by default
for (i = 1; i < 32; i++) begin for (i = 0; i < 32; i++) begin
memory[i] = 0; memory[i] = 0;
end end
end end
assign memory[0] = 32'h00000000;
assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory
always_comb begin always_comb begin
@ -29,7 +28,9 @@ always_comb begin
end end
always_ff @(negedge clk) begin always_ff @(negedge clk) begin
if (regwrite) begin if (writereg == 5'b00000) begin
// skip writing if rd is $0
end else if (regwrite) begin
case (opcode) case (opcode)
6'b100000: begin //lb, load byte 6'b100000: begin //lb, load byte
case (readdata1[1:0]) case (readdata1[1:0])