From 6687cb8e171e7d4c896846d2663c2a565d5af7b2 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Thu, 17 Dec 2020 09:43:04 -0800
Subject: [PATCH] Bring read signal low with clk during read cycle

---
 rtl/mips_cpu_bus.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v
index c120971..478766c 100644
--- a/rtl/mips_cpu_bus.v
+++ b/rtl/mips_cpu_bus.v
@@ -193,7 +193,7 @@ always_comb begin
             end
             2'b10: begin // connecting wires when in read state
                 address = harvard_data_address;
-                read = 1'b1;
+                read = clk_internal ? 1'b1 : 1'b0;
                 write = 1'b0;
                 byteenable = 4'b1111;
                 harvard_readdata = readdata;