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fixed naming convention errors in pc and harvard

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This commit is contained in:
Jeevaha Coelho 2020-12-15 03:16:01 -08:00
parent 2030a186cc
commit 5df8a72ca1
2 changed files with 4 additions and 6 deletions
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7
rtl/mips_cpu_harvard.v
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@ -20,13 +20,13 @@ module mips_cpu_harvard(
input logic[31:0] data_readdata//port from data memory out, going to the 'Write Register' port in regfile. input logic[31:0] data_readdata//port from data memory out, going to the 'Write Register' port in regfile.
); );
assign instr_address = in_pc_in; assign instr_address = out_pc_out;
assign data_address = out_ALURes; assign data_address = out_ALURes;
assign data_write = out_MemWrite; assign data_write = out_MemWrite;
assign data_read = out_MemRead; assign data_read = out_MemRead;
assign data_writedata = out_readdata2; assign data_writedata = out_readdata2;
logic[31:0] in_pc_in, out_pc_out = 32'hBFC00000, out_ALURes, out_readdata1, out_readdata2, in_B, in_writedata; logic[31:0] out_pc_out, out_ALURes, out_readdata1, out_readdata2, in_B, in_writedata;
logic[4:0] in_readreg1, in_readreg2, in_writereg, out_shamt, out_ALUOp; logic[4:0] in_readreg1, in_readreg2, in_writereg, out_shamt, out_ALUOp;
logic[5:0] in_opcode; logic[5:0] in_opcode;
logic out_ALUCond, out_RegWrite, out_ALUSrc, out_MemWrite, out_MemRead; logic out_ALUCond, out_RegWrite, out_ALUSrc, out_MemWrite, out_MemRead;
@ -81,9 +81,8 @@ mips_cpu_pc pc(
.instr(instr_readdata), //needed for branches and jumps .instr(instr_readdata), //needed for branches and jumps
.reg_readdata(out_readdata1), //needed for jump register .reg_readdata(out_readdata1), //needed for jump register
.pc_ctrl(out_PC), .pc_ctrl(out_PC),
.pc_in(out_pc_out),//what the pc will output on the next clock cycle taken from either: PC itself + 4(Normal/Default Operation); or 16-bit signed valued taken from Instr[15-0] sign extend to 32bit then shifted by 2 then added to PC + 4(Branch Operation); or 26-bit instruction address taken from J-type instr[25-0] shifted left by 2 then concatanated to form Jump Address (PC-region branch); or from the GPR rs.
//PC outputs //PC outputs
.pc_out(in_pc_in),//What the pc outputs at every clock edge that goes into the 'Read address' port of Instruction Memory. .pc_out(out_pc_out),//What the pc outputs at every clock edge that goes into the 'Read address' port of Instruction Memory.
.active(active) .active(active)
); );

3
rtl/mips_cpu_pc.v
View file

@ -2,7 +2,6 @@ module mips_cpu_pc(
input logic clk, input logic clk,
input logic rst, input logic rst,
input logic[1:0] pc_ctrl, input logic[1:0] pc_ctrl,
input logic[31:0] pc_in,
input logic[31:0] instr, input logic[31:0] instr,
input logic[31:0] reg_readdata, input logic[31:0] reg_readdata,
output logic[31:0] pc_out, output logic[31:0] pc_out,
@ -12,7 +11,7 @@ module mips_cpu_pc(
reg [31:0] pc_next, pc_lit_next; reg [31:0] pc_next, pc_lit_next;
initial begin initial begin
pc_out = pc_in; pc_out = 32'hBFC00000;
pc_next = pc_out + 32'd4; pc_next = pc_out + 32'd4;
end end