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Shorten testbench limit, remove custom bus script

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This commit is contained in:
Aadi Desai 2020-12-17 09:44:31 -08:00
parent e513096ed8
commit 5c29ec2be1
2 changed files with 1 additions and 68 deletions
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67
test/test_mips_cpu_custom_bus.sh
View file

@ -1,67 +0,0 @@
#!/bin/bash
# arithmetic
./test/test_mips_cpu_bus.sh rtl addu #Pass
./test/test_mips_cpu_bus.sh rtl addiu #Pass
./test/test_mips_cpu_bus.sh rtl subu #Pass
./test/test_mips_cpu_bus.sh rtl and #Pass
./test/test_mips_cpu_bus.sh rtl andi #Pass
./test/test_mips_cpu_bus.sh rtl or #Pass
./test/test_mips_cpu_bus.sh rtl ori #Pass
./test/test_mips_cpu_bus.sh rtl xor #Pass
./test/test_mips_cpu_bus.sh rtl xori #Pass
./test/test_mips_cpu_bus.sh rtl div #Pass
./test/test_mips_cpu_bus.sh rtl divu #pass
./test/test_mips_cpu_bus.sh rtl mthi #Pass
./test/test_mips_cpu_bus.sh rtl mtlo #Pass
./test/test_mips_cpu_bus.sh rtl mult #Pass
./test/test_mips_cpu_bus.sh rtl multu #Pass
# branches
./test/test_mips_cpu_bus.sh rtl beq #Pass
./test/test_mips_cpu_bus.sh rtl bgez #Pass
./test/test_mips_cpu_bus.sh rtl bgezal #Pass
./test/test_mips_cpu_bus.sh rtl bgtz #Pass
./test/test_mips_cpu_bus.sh rtl blez #Pass
./test/test_mips_cpu_bus.sh rtl bltz #Pass
./test/test_mips_cpu_bus.sh rtl bltzal #Pass
./test/test_mips_cpu_bus.sh rtl bne #Pass
# jumps
./test/test_mips_cpu_bus.sh rtl j #Pass
./test/test_mips_cpu_bus.sh rtl jalr #Pass
./test/test_mips_cpu_bus.sh rtl jal #Pass
./test/test_mips_cpu_bus.sh rtl jr #Pass
# shift
./test/test_mips_cpu_bus.sh rtl sll #Pass
./test/test_mips_cpu_bus.sh rtl srl #Pass
./test/test_mips_cpu_bus.sh rtl sra #Pass
./test/test_mips_cpu_bus.sh rtl srav #Pass
./test/test_mips_cpu_bus.sh rtl sllv #Pass
./test/test_mips_cpu_bus.sh rtl srlv #Pass
# load & store
./test/test_mips_cpu_bus.sh rtl lw #Pass
./test/test_mips_cpu_bus.sh rtl lb #Pass
./test/test_mips_cpu_bus.sh rtl lbu #Pass
./test/test_mips_cpu_bus.sh rtl lh #Pass
./test/test_mips_cpu_bus.sh rtl lhu #Pass
./test/test_mips_cpu_bus.sh rtl lui #Pass
./test/test_mips_cpu_bus.sh rtl lwl #Pass
./test/test_mips_cpu_bus.sh rtl lwr #Pass
./test/test_mips_cpu_bus.sh rtl sw #Pass
./test/test_mips_cpu_bus.sh rtl sb #Once switched to bus
./test/test_mips_cpu_bus.sh rtl sh #Once switched to bus
# set on less than **Branch delay slots dont work on these...
./test/test_mips_cpu_bus.sh rtl slti #Pass
./test/test_mips_cpu_bus.sh rtl sltiu #Pass
./test/test_mips_cpu_bus.sh rtl slt #Pass
./test/test_mips_cpu_bus.sh rtl sltu #Pass

2
testbench/mips_cpu_bus_tb.v
View file

@ -2,7 +2,7 @@ module mips_cpu_bus_tb;
parameter INSTR_INIT_FILE = ""; parameter INSTR_INIT_FILE = "";
parameter DATA_INIT_FILE = ""; parameter DATA_INIT_FILE = "";
parameter TIMEOUT_CYCLES = 1000; // Timeout cycles are higher to account for memory stall delays parameter TIMEOUT_CYCLES = 100; // Timeout cycles are higher to account for memory stall delays
logic clk, reset, active, write, read, waitrequest; logic clk, reset, active, write, read, waitrequest;
logic[31:0] address, register_v0, writedata, readdata; logic[31:0] address, register_v0, writedata, readdata;