From 4ff160db1a5c6affd90a3f346dede4430da9450a Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@imperial.ac.uk>
Date: Wed, 16 Dec 2020 05:04:45 +0000
Subject: [PATCH] Fix syntax errors from mult/div

---
 rtl/mips_cpu_alu.v     | 6 +++---
 rtl/mips_cpu_control.v | 4 ++--
 rtl/mips_cpu_harvard.v | 6 +++---
 rtl/mips_cpu_pc.v      | 2 +-
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/rtl/mips_cpu_alu.v b/rtl/mips_cpu_alu.v
index cf49895..22b2967 100644
--- a/rtl/mips_cpu_alu.v
+++ b/rtl/mips_cpu_alu.v
@@ -99,7 +99,7 @@ initial begin
   Lo <= 32'd0;
 end
 
-  always_comb begin
+  always @(*) begin
     assign ALUOps = ALUOp;
     case(ALUOps)
       ADD: begin
@@ -216,11 +216,11 @@ end
           end
           
       end
-
+/*
       PAS: begin
         ALURes = A;
       end
-
+*/
       SLT: begin
         if ($signed(A) < $signed(B)) begin
           ALURes = 1;
diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v
index 40b5aa4..e5fff07 100644
--- a/rtl/mips_cpu_control.v
+++ b/rtl/mips_cpu_control.v
@@ -120,9 +120,9 @@ always @(*) begin
         $display("Memory read disabled");
     end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)))begin
         CtrlMemtoReg = 3'd2;//write data port of regfile is fed from PC + 8
-    end else if ((op==SPECIAL)&&(funct == MTHI)))begin
+    end else if ((op==SPECIAL)&&(funct == MTHI))begin
         CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi
-    end else if ((op==SPECIAL)&&(funct == MTLO)))begin
+    end else if ((op==SPECIAL)&&(funct == MTLO))begin
         CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo
     end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
 
diff --git a/rtl/mips_cpu_harvard.v b/rtl/mips_cpu_harvard.v
index b54f787..fa6ffd5 100644
--- a/rtl/mips_cpu_harvard.v
+++ b/rtl/mips_cpu_harvard.v
@@ -26,10 +26,10 @@ assign data_write = out_MemWrite;
 assign data_read = out_MemRead;
 assign data_writedata = out_readdata2;
 
-logic[31:0] out_pc_out, out_ALURes, out_readdata1, out_readdata2, in_B, in_writedata;
+logic[31:0] out_pc_out, out_ALURes, out_readdata1, out_readdata2, in_B, in_writedata, out_ALUHi, out_ALULo;
 logic[4:0]  in_readreg1, in_readreg2, in_writereg, out_shamt, out_ALUOp;
 logic[5:0]  in_opcode;
-logic out_ALUCond, out_RegWrite, out_ALUSrc, out_MemWrite, out_MemRead;
+logic out_ALUCond, out_RegWrite, out_ALUSrc, out_MemWrite, out_MemRead, out_SpcRegWriteEn;
 logic[1:0] out_RegDst, out_PC;
 logic[2:0] out_MemtoReg;
 
@@ -140,7 +140,7 @@ mips_cpu_alu alu(
     .ALUCond(out_ALUCond), //condition used by control to decide on branch instructions.
     .ALURes(out_ALURes), //output/result of operation that goes to either: 'Address' port of Data Memory; or 'Write Data' port of the register file.
     .ALUHi(out_ALUHi), //Special register Hi output to be used for MFHI instructions - feeds in_writedata.
-    .ALULo(out_ALULo), //Special register Hi output to be used for MFLO instructions - feeds in_writedata.
+    .ALULo(out_ALULo) //Special register Hi output to be used for MFLO instructions - feeds in_writedata.
 );
 
 endmodule
diff --git a/rtl/mips_cpu_pc.v b/rtl/mips_cpu_pc.v
index 3e1d8e0..7531c00 100644
--- a/rtl/mips_cpu_pc.v
+++ b/rtl/mips_cpu_pc.v
@@ -30,7 +30,7 @@ always_ff @(posedge clk) begin
 end
 
 
-always_comb begin
+always @(*) begin
 		case(pc_ctrl)
 			2'd1: begin // Branch
 				pc_next = pc_out + 32'd4 + {{14{instr[15]}},instr[15:0],2'b00};