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https://github.com/supleed2/ELEC50010-IAC-CW.git
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Add testbench related files
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4
inputs/addu.txt
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4
inputs/addu.txt
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350C0003
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350D0005
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018D5021
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01000008
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77
inputs/reference.txt
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77
inputs/reference.txt
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== Instruction ==
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C code
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Assembly code
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Hex code
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Reference Output
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================
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== ADDIU Add immediate unsigned (no overflow) ==
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== ADDU Add unsigned (no overflow) ==
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int main(void) {
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int a = 3 + 5;
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}
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ORI $4,$0,3
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ORI $5,$0,5
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ADDU $2,$4,$5
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JR $0
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350C0003
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350D0005
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018D5021
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01000008
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register_vo = 8
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== AND Bitwise and ==
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ANDI Bitwise and immediate
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BEQ Branch on equal
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BGEZ Branch on greater than or equal to zero
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BGEZAL Branch on non-negative (>=0) and link
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BGTZ Branch on greater than zero
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BLEZ Branch on less than or equal to zero
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BLTZ Branch on less than zero
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BLTZAL Branch on less than zero and link
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BNE Branch on not equal
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DIV Divide
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DIVU Divide unsigned
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J Jump
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JALR Jump and link register
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JAL Jump and link
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JR Jump register
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LB Load byte
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LBU Load byte unsigned
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LH Load half-word
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LHU Load half-word unsigned
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LUI Load upper immediate
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LW Load word
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LWL Load word left
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LWR Load word right
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MTHI Move to HI
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MTLO Move to LO
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MULT Multiply
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MULTU Multiply unsigned
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OR Bitwise or
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ORI Bitwise or immediate
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SB Store byte
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SH Store half-word
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SLL Shift left logical
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SLLV Shift left logical variable
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SLT Set on less than (signed)
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SLTI Set on less than immediate (signed)
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SLTIU Set on less than immediate unsigned
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SLTU Set on less than unsigned
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SRA Shift right arithmetic
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SRAV Shift right arithmetic
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SRL Shift right logical
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SRLV Shift right logical variable
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SUBU Subtract unsigned
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SW Store word
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XOR Bitwise exclusive or
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XORI Bitwise exclusive or immediate
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@ -42,7 +42,7 @@ module mips_cpu_memory(
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//Load contents from file if specified
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//Load contents from file if specified
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if (RAM_INIT_FILE != "") begin
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if (RAM_INIT_FILE != "") begin
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$display("RAM : INIT : Loading RAM contents from %s", RAM_INIT_FILE);
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$display("RAM : INIT : Loading RAM contents from %s", RAM_INIT_FILE);
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$readmemh(RAM_INIT_FILE, memory);
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$readmemh(RAM_INIT_FILE, memory[3217031168:0]);
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end
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end
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end
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end
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@ -1,4 +1,55 @@
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#!/bin/bash
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#!/bin/bash
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# should not create any files in the rtl dir
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# should not create any files in the rtl dir
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# but auxiliary files / dirs can be utilised
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# but auxiliary files / dirs can be utilised
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# Source File & Source Directory Parsing
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SRC_DIR=${1?Error: no source directory given in argument}; # e.g. ./rtl
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SRC=$(ls ${SRC_DIR} | grep -E "harvard|memory|alu|regfile|pc|control");
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SRC_TEMP="";
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for src in ${SRC}
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do
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SRC_TEMP+=${SRC_DIR}/${src}" ";
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done
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SRC=${SRC_TEMP}
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echo ${SRC}
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# Instruction Argument
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INSTR=${2:-"No instruction specified: running all testcases"}; # e.g. addiu
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echo ${INSTR};
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# Start Testing
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if [[ ${INSTR} == "No instruction specified: running all testcases" ]];
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then
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# All Testcase Files
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TESTCASES=$(ls ./inputs | grep ".hex.txt");
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echo ${TESTCASES}
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for TESTCASE in ${TESTCASES}
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do
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# Run Each Testcase File
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echo ${TESTCASE}
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# iverilog -g 2012 \
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# -s mips_cpu_harvard_tb \
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# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/"${TESTCASE}\" \
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# -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
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# ${SRC}
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done
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else
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echo "ELSE";
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# Run Testcase File Of Specified Instruction
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# iverilog -g 2012 \
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# -s mips_cpu_harvard_tb \
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# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.hex.txt\" \
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# -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
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# ${SRC}
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fi
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#/mnt/c/Windows/System32/cmd.exe /C \ # need this to run verilog on windows
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#iverilog -g 2012 \
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# -s mips_cpu_harvard_tb \
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# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/addiu.hex.txt\" \
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# -o program/mips_cpu_harvard_tb testbench/mips_cpu_harvard_tb.v test/mips_cpu_harvard.v \
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# test/mips_cpu_control.v test/mips_cpu_alu.v test/mips_cpu_memory.v test/mips_cpu_regfile.v test/mips_cpu_pc.v
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61
testbench/mips_cpu_bus_tb.v
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61
testbench/mips_cpu_bus_tb.v
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module CPU_MU0_delay1_tb;
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timeunit 1ns / 10ps;
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parameter RAM_INIT_FILE = "test/01-binary/countdown.hex.txt";
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parameter TIMEOUT_CYCLES = 10000;
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logic clk;
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logic rst;
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logic running;
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logic[11:0] address;
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logic write;
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logic read;
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logic[15:0] writedata;
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logic[15:0] readdata;
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RAM_16x4096_delay1 #(RAM_INIT_FILE) ramInst(clk, address, write, read, writedata, readdata);
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CPU_MU0_delay1 cpuInst(clk, rst, running, address, write, read, writedata, readdata);
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// Generate clock
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initial begin
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clk=0;
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repeat (TIMEOUT_CYCLES) begin
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#10;
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clk = !clk;
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#10;
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clk = !clk;
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end
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$fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES);
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end
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initial begin
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rst <= 0;
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@(posedge clk);
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rst <= 1;
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@(posedge clk);
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rst <= 0;
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@(posedge clk);
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assert(running==1)
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else $display("TB : CPU did not set running=1 after reset.");
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while (running) begin
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@(posedge clk);
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end
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$display("TB : finished; running=0");
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$finish;
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end
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endmodule
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51
testbench/mips_cpu_harvard_tb.v
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51
testbench/mips_cpu_harvard_tb.v
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module mips_cpu_harvard_tb;
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timeunit 1ns / 10ps;
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parameter RAM_INIT_FILE = "inputs/";
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parameter TIMEOUT_CYCLES = 10000;
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logic clk, clk_enable, reset, active;
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logic[31:0] register_v0;
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logic[31:0] instr_address, instr_readdata;
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logic data_read, data_write;
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logic[31:0] data_readdata, data_writedata, data_address;
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mips_cpu_memory #(RAM_INIT_FILE) ramInst(clk, data_address, data_write, data_read, data_writedata, data_readdata, instr_address, instr_readdata);
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mips_cpu_harvard cpuInst(clk, reset, active, register_v0, clk_enable, instr_address, instr_readdata, data_address, data_write, data_read, data_writedata, data_readdata);
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// Generate clock
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initial begin
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clk=0;
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repeat (TIMEOUT_CYCLES) begin
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#10;
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clk = !clk;
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#10;
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clk = !clk;
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end
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$fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES);
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end
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initial begin
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reset <= 0;
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@(posedge clk);
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reset <= 1;
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@(posedge clk);
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reset <= 0;
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@(posedge clk);
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assert(running==1)
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else $display("TB : CPU did not set running=1 after reset.");
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while (running) begin
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@(posedge clk);
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end
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$display("TB : finished; running=0");
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$finish;
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end
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endmodule
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