Updated bus tb to match harvard tb

This commit is contained in:
Aadi Desai 2020-12-16 20:05:00 +00:00
parent a31ed073e1
commit 2f9b08a363

View file

@ -1,26 +1,42 @@
module mips_cpu_bus_tb; module mips_cpu_bus_tb;
timeunit 1ns / 10ps;
parameter RAM_INIT_FILE = "test/01-binary/countdown.hex.txt"; parameter INSTR_INIT_FILE = "inputs/addiu.txt";
parameter TIMEOUT_CYCLES = 10000; parameter DATA_INIT_FILE = "inputs/addiu.data.txt";
parameter TIMEOUT_CYCLES = 1000; // Timeout cycles are higher to account for memory stall delays
logic clk; logic clk, reset, active, write, read, waitrequest;
logic rst; logic[31:0] address, register_v0, writedata, readdata;
logic[3:0] byteenable;
logic running; mips_cpu_bus_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) memInst( //Avalon memory mapped bus controller (slave)
.clk(clk), // clk input to mem
.address(address), // addr input to mem
.write(write), // write flag input
.read(read), // read flag input
.waitrequest(waitrequest), // mem stall output
.writedata(writedata), // data to be written
.byteenable(byteenable), // byteenable bus for writes
.readdata(readdata) // read output port
);
logic[11:0] address; mips_cpu_bus cpuInst(
logic write; .clk(clk), // clk input to cpu wrapper
logic read; .reset(reset), // reset input
logic[15:0] writedata; .active(active), // active output flag
logic[15:0] readdata; .register_v0(register_v0), // debug $2 or $v0 output bus
.address(address), // mem addr output
.write(write), // mem write output flag
.read(read), // mem read output flag
.waitrequest(waitrequest), // mem stall input flag
.writedata(writedata), // data to write to mem output
.byteenable(byteenable), // bytes to write output
.readdata(readdata) // data from mem input
);
RAM_16x4096_delay1 #(RAM_INIT_FILE) ramInst(clk, address, write, read, writedata, readdata); // Setup and clock
initial begin
CPU_MU0_delay1 cpuInst(clk, rst, running, address, write, read, writedata, readdata); $dumpfile("mips_cpu_bus.vcd");
$dumpvars(0,mips_cpu_bus_tb);
// Generate clock
initial begin
clk=0; clk=0;
repeat (TIMEOUT_CYCLES) begin repeat (TIMEOUT_CYCLES) begin
@ -31,31 +47,33 @@ module mips_cpu_bus_tb;
end end
$fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES); $fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES);
end
initial begin
reset <= 1;
@(posedge clk);
reset <= 0;
@(posedge clk);
assert(active==1)
else $display("TB : CPU did not set active=1 after reset.");
while (active) begin
//$display("Clk: %d", clk);
@(posedge clk);
//$display("Register v0: %d", register_v0);
//$display("Reg File Write data: %d", cpuInst.in_writedata);
$display("Reg File Out Read data: %h", cpuInst.mips_cpu_harvard.out_readdata1);
$display("Reg File opcode: %b", cpuInst.mips_cpu_harvard.regfile.opcode);
//$display("ALU output: %h", cpuInst.out_ALURes);
//$display("ALU input B: %h", cpuInst.alu.B);
end end
initial begin
rst <= 0;
@(posedge clk); @(posedge clk);
rst <= 1; $display("TB: CPU Halt; active=0");
$display("Output:");
@(posedge clk); $display("%d",register_v0);
rst <= 0;
@(posedge clk);
assert(running==1)
else $display("TB : CPU did not set running=1 after reset.");
while (running) begin
@(posedge clk);
end
$display("TB : finished; running=0");
$finish; $finish;
end
end
endmodule endmodule