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Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into jl7719
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jl7719
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2e17e38957
BIN
Instructions.xlsx
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BIN
Instructions.xlsx
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@ -1,18 +1,23 @@
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== Instruction ==
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C code
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Assembly code
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Hex code
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Reference Output
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================
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ADDIU Add immediate unsigned (no overflow)
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==ADDIU Add immediate unsigned (no overflow)==
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ORI $4,$0,0xA
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ADDIU $2,$4,20
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JR $0
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3404000a
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24820014
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00000008
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register_v0 = 30
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== ADDU Add unsigned (no overflow) ==
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int main(void) {
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int a = 3 + 5;
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}
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ORI $4,$0,3
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ORI $5,$0,5
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ADDU $2,$4,$5
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@ -511,73 +516,277 @@ JR $0
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register_v0 = 0x12345678
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// DIVU Divide unsigned
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==MTHI Move to HI==
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// DIV Divide
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ori $4, $0, 5
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mthi $4
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mfhi $2
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jr $0
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//MFHI Move from Hi
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34040005
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00800011
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00001010
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00000008
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//MFLO Move from lo
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register_v0 = 5
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//MTHI Move to HI
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==MTLO Move to LO==
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//MTLO Move to LO
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ori $4, $0, 5
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mtlo $4
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mflo $2
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jr $0
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//MULT Multiply**
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34040005
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00800013
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00001012
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00000008
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//MULTU Multiply unsigned**
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register_v0 = 5
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//OR Bitwise or
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==MULT Multiply==
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//ORI Bitwise or immediate
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ori $4, $0, 4
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ori $5, $0, 3
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mult $4, $5
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mflo $2
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jr $0
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//SB Store byte
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34040004
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34050003
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00850018
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00001012
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00000008
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//SH Store half-word**
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register_v0 = 12
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//SLL Shift left logical
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==MULTU Multiply unsigned==
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//SLLV Shift left logical variable **
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ori $4, $0, 4
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ori $5, $0, 3
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multu $4, $5
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mflo $2
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jr $0
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34040004
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34050003
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00850019
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00001012
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00000008
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register_v0 = 12
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==OR Bitwise or==
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ori $4, $0, 5
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ori $5, $0, 3
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or $2, $4, $5
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jr $0
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34040005
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34050003
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00851025
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00000008
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register_v0 = 7
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==ORI Bitwise or immediate==
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ori $2, $0, 3
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ori $2, $0, 5
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jr $0
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34020003
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00000008
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34020005
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register_v0 = 7
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==SB Store byte==
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ori $4, $0, 1029
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ori $5, $0, 1
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sb $4, 1($5)
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jr $0
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34040405
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34050001
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a0a40001
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00000008
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register_v0 = 5
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SH Store half-word
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==SLL Shift left logical==
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ori $4,$0,3
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sll $2,$4,2
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jr $0
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34040003
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00041080
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00000008
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register_v0 = 16
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==SLLV Shift left logical variable==
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ori $4,$0,2
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ori $5,$0,3
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sllv $2,$5,$4
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jr $0
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34040002
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34050003
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register_v0 = 16
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//SLT Set on less than (signed)
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//SLTI Set on less than immediate (signed)
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==SLTI Set on less than immediate (signed)==
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//SLTIU Set on less than immediate unsigned
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ori $4, $0, 10
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slti $2, $4, 9
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jr $0
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//SLTU Set on less than unsigned
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3404000a
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28820009
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00000008
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//SRA Shift right arithmetic
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register_v0 = 0
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//SRAV Shift right arithmetic**
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==SLTIU Set on less than immediate unsigned==
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//SRL Shift right logical
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ori $4, $0, 10
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sltiu $2, $4, 9
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jr $0
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//SRLV Shift right logical variable**
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3404000a
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2c820009
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00000008
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//SUBU Subtract unsigned
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register_v0 = 0
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//SW Store word
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==SLTU Set on less than unsigned==
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ori $4, $0, 0xFFFF 3404FFFF
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ori $5, $0, 0x1008 34051008
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sw $4, 4($5) ACA40004
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ori $5, $0, 0x100C 3405100C
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lw $2, 0($5) 8CA20000
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jr $0 00000008
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ori $4, $0, 10
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ori $5, $0, 9
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sltu $2, $4, $5
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jr $0
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ori $4, $0, 0x1234
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3404000a
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34050009
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0085102b
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00000008
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register_v0 = 0
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==SRA Shift right arithmetic==
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ori $4,$0,-2147483647
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sra $2,$4,$2
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jr $0
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register 0 = -536870912 (first 3 bits high - rest low)
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34040001
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00041003
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00000008
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==SRAV Shift right arithmetic==
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ori $4, $0, 4
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ori $5,$0,0xF000
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srav $2,$5,$4
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SRAv $v0 $a1 $a0
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jr $0
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register 0 = -536870912 (first 3 bits high - rest low)
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34040004
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3405F000
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==SRL Shift right logical==
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ori $4,$0,-2147483647
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srl $2,$4,$2
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jr $0
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register 0 = 536870912 (2^29)
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34040001
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00041002
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00000008
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==SRLV Shift right logical variable==
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ori $4,$0,2
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ori $5,$0,16
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srlv $2,$5,$4
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jr $0
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34040002
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34050010
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00851006
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00000008
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register_v0 = 3
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==SUBU Subtract unsigned==
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ori $4,$0,5
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ori $5,$0,3
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subu $2,$4,$5
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jr $0
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34040005
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34050003
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00851023
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00000008
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register_v0 = 2
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==SW Store word==
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ori $4, $0, 0xFFFF
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ori $5, $0, 0x1008
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sw $4, 0($5)
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sw $4, 4($5)
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ori $5, $0, 0x100C
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lw $2, 0($5)
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jr $0
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3404FFFF
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34051008
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ACA40000
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ACA40004
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3405100C
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8CA20000
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00000008
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//XOR Bitwise exclusive or
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register_v0 = 0x0000FFFF
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//XORI Bitwise exclusive or immediate
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==XOR Bitwise exclusive or==
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ori $4, $0, 5
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ori $5, $0, 2
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xor $2, $4, $5
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jr $0
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34040005
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34050002
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00851026
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00000008
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register_v0 = 7
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==XORI Bitwise exclusive or immediate==
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ori $4,$0,5
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xori $2,$4,0xF
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jr $0
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34040005
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3882000F
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00000008
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register_v0 = 10
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@ -5,7 +5,7 @@ module mips_cpu_alu(
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input logic [4:0] shamt, //5-bit input used to specify shift amount for shift operations. Taken directly from the R-type instruction (Non-Variable) or from
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output logic ALUCond, //If a relevant condition is met, this output goes high(Active High). Note: Relevant as in related to current condition being tested.
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output logic signed[31:0] ALURes // The ouput of the ALU
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output logic[31:0] ALURes // The ouput of the ALU
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);
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/*
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@ -77,19 +77,19 @@ Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming
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assign ALUOps = ALUOp;
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case(ALUOps)
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ADD: begin
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ALURes = $signed(A) + $signed(B);
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$signed(ALURes) = $signed(A) + $signed(B);
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end
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SUB: begin
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ALURes = $signed(A) - $signed(B) ;
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$signed(ALURes) = $signed(A) - $signed(B) ;
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end
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MUL: begin
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ALURes = $signed(A) * $signed(B);
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$signed(ALURes) = $signed(A) * $signed(B);
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end
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DIV: begin
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ALURes = $signed(A) / $signed(B);
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$signed(ALURes) = $signed(A) / $signed(B);
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end
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AND: begin
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@ -121,11 +121,11 @@ Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming
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end
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SRA: begin
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ALURes = $signed(B) >>> shamt;
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$signed(ALURes) = $signed(B) >>> shamt;
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end
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SRAV: begin
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ALURes = $signed(B) >>> A;
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$signed(ALURes) = $signed(B) >>> A;
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end
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EQ: begin
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@ -205,11 +205,11 @@ Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming
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end
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MULU: begin
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ALURes = A * B;
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$signed(ALURes) = $signed(A) * $signed(B);
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end
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DIVU: begin
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ALURes = A / B;
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$signed(ALURes) = $signed(A) / $signed(B);
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end
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endcase
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