From 7ffd8fb40026958c0f8b2171b224aa13c2ed701a Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@ic.ac.uk>
Date: Fri, 11 Dec 2020 15:17:43 +0900
Subject: [PATCH] Add testcases and ref outputs for addiu, and, andi

---
 inputs/addiu.ref.txt  | 1 +
 inputs/addiu.txt      | 3 +++
 inputs/and.ref.txt    | 1 +
 inputs/and.txt        | 4 ++++
 inputs/andi.ref.txt   | 1 +
 inputs/andi.txt       | 5 +++++
 rtl/mips_cpu_memory.v | 2 +-
 7 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 inputs/addiu.ref.txt
 create mode 100644 inputs/addiu.txt
 create mode 100644 inputs/and.ref.txt
 create mode 100644 inputs/and.txt
 create mode 100644 inputs/andi.ref.txt
 create mode 100644 inputs/andi.txt

diff --git a/inputs/addiu.ref.txt b/inputs/addiu.ref.txt
new file mode 100644
index 0000000..8580e7b
--- /dev/null
+++ b/inputs/addiu.ref.txt
@@ -0,0 +1 @@
+30
\ No newline at end of file
diff --git a/inputs/addiu.txt b/inputs/addiu.txt
new file mode 100644
index 0000000..62290ae
--- /dev/null
+++ b/inputs/addiu.txt
@@ -0,0 +1,3 @@
+3404000a
+24820014
+00000008
\ No newline at end of file
diff --git a/inputs/and.ref.txt b/inputs/and.ref.txt
new file mode 100644
index 0000000..9a03714
--- /dev/null
+++ b/inputs/and.ref.txt
@@ -0,0 +1 @@
+10
\ No newline at end of file
diff --git a/inputs/and.txt b/inputs/and.txt
new file mode 100644
index 0000000..24529d7
--- /dev/null
+++ b/inputs/and.txt
@@ -0,0 +1,4 @@
+3404000A
+3405000F
+00851024
+00000008
\ No newline at end of file
diff --git a/inputs/andi.ref.txt b/inputs/andi.ref.txt
new file mode 100644
index 0000000..7813681
--- /dev/null
+++ b/inputs/andi.ref.txt
@@ -0,0 +1 @@
+5
\ No newline at end of file
diff --git a/inputs/andi.txt b/inputs/andi.txt
new file mode 100644
index 0000000..74b3184
--- /dev/null
+++ b/inputs/andi.txt
@@ -0,0 +1,5 @@
+34040005
+3082000f
+00000008
+00000000
+00000000
\ No newline at end of file
diff --git a/rtl/mips_cpu_memory.v b/rtl/mips_cpu_memory.v
index b87312c..13b4015 100644
--- a/rtl/mips_cpu_memory.v
+++ b/rtl/mips_cpu_memory.v
@@ -45,7 +45,7 @@ module mips_cpu_memory(
 
     //Synchronous write path
     always_ff @(posedge clk) begin
-        $display("Instruction Read: %h", instr_readdata);
+        //$display("Instruction Read: %h", instr_readdata);
         //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
         if (!data_read & data_write) begin              //cannot read and write to memory in the same cycle
             if (instr_address != data_address) begin    //cannot modify the instruction being read