Minor sytax corrections

This commit is contained in:
Ibrahim 2020-12-02 13:35:47 +00:00
parent 56dfe9e1e8
commit 2a6d87c7b8

View file

@ -112,19 +112,19 @@ module mips_cpu_alu(
end
SLL: begin
ALUOut = B << shamt //Shamt is instruction read data [10:6]
ALUOut = B << shamt; //Shamt is instruction read data [10:6]
end
SRL: begin
ALUOut = B >> shamt //Shamt is instruction read data [10:6]
ALUOut = B >> shamt; //Shamt is instruction read data [10:6]
end
SLLV: begin
ALUOut = B << A
ALUOut = B << A;
end
SRLV: begin
ALUOut = B >> A
ALUOut = B >> A;
end
AND: begin