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Minor sytax corrections
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@ -112,19 +112,19 @@ module mips_cpu_alu(
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end
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SLL: begin
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ALUOut = B << shamt //Shamt is instruction read data [10:6]
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ALUOut = B << shamt; //Shamt is instruction read data [10:6]
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end
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SRL: begin
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ALUOut = B >> shamt //Shamt is instruction read data [10:6]
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ALUOut = B >> shamt; //Shamt is instruction read data [10:6]
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end
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SLLV: begin
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ALUOut = B << A
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ALUOut = B << A;
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end
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SRLV: begin
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ALUOut = B >> A
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ALUOut = B >> A;
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end
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AND: begin
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