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Minor sytax corrections

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Ibrahim 2020-12-02 13:35:47 +00:00
parent 56dfe9e1e8
commit 2a6d87c7b8
1 changed files with 4 additions and 4 deletions
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8
rtl/mips_cpu_alu.v
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@ -112,19 +112,19 @@ module mips_cpu_alu(
end end
SLL: begin SLL: begin
ALUOut = B << shamt //Shamt is instruction read data [10:6] ALUOut = B << shamt; //Shamt is instruction read data [10:6]
end end
SRL: begin SRL: begin
ALUOut = B >> shamt //Shamt is instruction read data [10:6] ALUOut = B >> shamt; //Shamt is instruction read data [10:6]
end end
SLLV: begin SLLV: begin
ALUOut = B << A ALUOut = B << A;
end end
SRLV: begin SRLV: begin
ALUOut = B >> A ALUOut = B >> A;
end end
AND: begin AND: begin