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Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into main

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Ibrahim 2020-12-15 13:38:04 +00:00
parent 6519be9a9e
commit 26ccff5057
10 changed files with 93 additions and 22 deletions
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5
inputs/reference/divquotient.txt Normal file
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@ -0,0 +1,5 @@
34040004
34050003
0085001A
00001012
00000008

5
inputs/reference/divremainder.txt Normal file
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@ -0,0 +1,5 @@
34040004
34050003
0085001A
00001010
00000008

5
inputs/reference/divuquotient Normal file
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@ -0,0 +1,5 @@
34040004
34050003
0085001B
00001012
00000008

5
inputs/reference/divuremainder.txt Normal file
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@ -0,0 +1,5 @@
34040004
34050003
0085001B
00001010
00000008

72
inputs/reference/ibrahimreference.txt
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@ -111,8 +111,8 @@ register 0 = 3
34040002 34040002
34050010 34050010
////// 00851006
////// 00000008
=============== SRL Shift right logical ============== =============== SRL Shift right logical ==============
@ -147,8 +147,8 @@ register 0 = -536870912 (first 3 bits high - rest low)
34040002 34040002
34050001 34050001
//////// 00851007
/////// 00000008
====== SRA Shift right arithmetic ========== ====== SRA Shift right arithmetic ==========
@ -252,8 +252,8 @@ register 0 = 16
34040002 34040002
34050003 34050003
////// 00851004
////// 00000008
======= SLL Shift left logical ====== ======= SLL Shift left logical ======
@ -445,37 +445,83 @@ $HI = 5
==================== SH Store half-word ======= ==================== SH Store half-word =======
///////// lui $4, 3
ori $5, $0, 3
or $6, $4, $5
sh $6, 1($1)
jr $0
3c040003
34050003
00853025
A4260001
00000008
======== DIV Divide ====== ======== DIV Divide quotient ======
ori $4, $0, 4 ori $4, $0, 4
ori $5, $0, 3 ori $5, $0, 3
div $4, $5 div $4, $5
mflo $2
jr $0 jr $0
$LO = 1 register v0 = 1
$HI = 1
34040004 34040004
34050003 34050003
0085001A 0085001A
00001012
00000008 00000008
========= DIVU Divide unsigned ===== ======== DIV Divide remainder ======
ori $4, $0, 4
ori $5, $0, 3
div $4, $5
mfhi $2
jr $0
register v0 = 1
34040004
34050003
0085001A
00001010
00000008
========= DIVU Divide unsigned quotient =====
ori $4, $0, 4 ori $4, $0, 4
ori $5, $0, 3 ori $5, $0, 3
divu $4, $5 divu $4, $5
mflo $2
jr $0 jr $0
$LO = 1 register_vo = 1
$HI = 1
34040004 34040004
34050003 34050003
0085001B 0085001B
00001012
00000008
========= DIVU Divide unsigned remainder =====
ori $4, $0, 4
ori $5, $0, 3
divu $4, $5
mfhi $2
jr $0
register_vo = 1
34040004
34050003
0085001B
00001010
00000008 00000008

6
inputs/reference/reference.txt
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@ -537,7 +537,7 @@ register_v0 = 0x12345678
//SLL Shift left logical //SLL Shift left logical
//SLLV Shift left logical variable ** //SLLV Shift left logical variable
//SLT Set on less than (signed) //SLT Set on less than (signed)
@ -549,11 +549,11 @@ register_v0 = 0x12345678
//SRA Shift right arithmetic //SRA Shift right arithmetic
//SRAV Shift right arithmetic** //SRAV Shift right arithmetic
//SRL Shift right logical //SRL Shift right logical
//SRLV Shift right logical variable** //SRLV Shift right logical variable
//SUBU Subtract unsigned //SUBU Subtract unsigned

5
inputs/reference/sh.txt Normal file
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@ -0,0 +1,5 @@
3c040003
34050003
00853025
A4260001
00000008

4
inputs/sllv.txt
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@ -1,4 +1,4 @@
34040002 34040002
34050003 34050003
////// 00851004
////// 00000008

4
inputs/srav.txt
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@ -1,4 +1,4 @@
34040002 34040002
34050001 34050001
//////// 00851007
/////// 00000008

4
inputs/srlv.txt
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@ -1,4 +1,4 @@
34040002 34040002
34050010 34050010
////// 00851006
////// 00000008