supleed2/ELEC50010-IAC-CW
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All instructions except load finished - some test cases may need changing upon review

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Ibrahim 2020-12-10 19:39:04 +00:00
parent 04b1ed4fed
commit 1bf7b5d40e
16 changed files with 270 additions and 12 deletions
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4
inputs/div.txt Normal file
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34040004
34050003
0085001A
00000008

4
inputs/divu.txt Normal file
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34040004
34050003
0085001B
00000008

207
inputs/ibrahimreference.txt
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@ -272,3 +272,210 @@ register 0 = 16
34040003
00041080
00000008
======== SB Store byte =======
ori $4, $0, 1029
ori $5, $0, 1
sb $4, 1($5)
jr $0
register 0 = 5
34040405
34050001
a0a40001
00000008
======== ORI Bitwise or immediate ===
ori $4,$0,3
jr $0
register a0 = 3
34040003
00000008
======== OR Bitwise or ===
int main(){
int a =5;
int b= 3;
int c = 5 | 3;
return 0;
}
ori $4, $0, 5
ori $5, $0, 3
or $2, $4, $5
jr $0
34040005
34050003
00851025
00000008
register 0 = 7
======= MULT Multiply =====
ori $4, $0, 4
ori $5, $0, 3
mult $4, $5
jr $0
$LO = 12
34040004
34050003
00850018
00000008
======= MULT Multiply =====
ori $4, $0, 4
ori $5, $0, 3
mult $4, $5
mflo $2
jr $0
register v0 = 12
34040004
34050003
00850018
00001012
00000008
======= MULTU Multiply unsigned =====
ori $4, $0, 4
ori $5, $0, 3
multu $4, $5
jr $0
$LO = 12
34040004
34050003
00850019
00000008
======= MULTU Multiply unsigned =====
ori $4, $0, 4
ori $5, $0, 3
multu $4, $5
mflo $2
jr $0
$2 = 12
34040004
34050003
00850019
00001012
00000008
======= MFLO Move from lo ======
ori $4, $0, 4
ori $5, $0, 3
multu $4, $5
mflo $2
jr $0
$2 = 12
34040004
34050003
00850019
00001012
00000008
=========== MFHI Move from Hi ==========
ori $4, $0, 3
mthi $4
mfhi $2
jr $0
register v0 = 3
34040003
00800011
00001010
00000008
======== MTHI Move to HI ====
ori $4, $0, 5
mthi $4
jr $0
$HI = 5
34040005
00800011
00000008
======= MTLO Move to LO ===
ori $4, $0, 5
mtlo $4
jr $0
$HI = 5
34040005
00800013
00000008
==================== SH Store half-word =======
/////////
======== DIV Divide ======
ori $4, $0, 4
ori $5, $0, 3
div $4, $5
jr $0
$LO = 1
$HI = 1
34040004
34050003
0085001A
00000008
========= DIVU Divide unsigned =====
ori $4, $0, 4
ori $5, $0, 3
divu $4, $5
jr $0
$LO = 1
$HI = 1
34040004
34050003
0085001B
00000008

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inputs/mfhi.txt Normal file
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34040003
00800011
00001010
00000008

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inputs/mflo.txt Normal file
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@ -0,0 +1,5 @@
34040004
34050003
00850019
00001012
00000008

3
inputs/mthi.txt Normal file
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@ -0,0 +1,3 @@
34040005
00800011
00000008

3
inputs/mtlo.txt Normal file
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@ -0,0 +1,3 @@
34040005
00800013
00000008

5
inputs/mult.txt Normal file
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@ -0,0 +1,5 @@
34040004
34050003
00850018
00001012
00000008

4
inputs/multcurrent.txt Normal file
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@ -0,0 +1,4 @@
34040004
34050003
00850018
00000008

5
inputs/multu.txt Normal file
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@ -0,0 +1,5 @@
34040004
34050003
00850019
00001012
00000008

4
inputs/multucurrent.txt Normal file
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@ -0,0 +1,4 @@
34040004
34050003
00850019
00000008

4
inputs/or.txt Normal file
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@ -0,0 +1,4 @@
34040005
34050003
00851025
00000008

6
inputs/ori.txt
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@ -1,8 +1,2 @@
34040003
00000008
00000000
00000000
00000000
00000000
00000000
00000000

20
inputs/reference.txt
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@ -330,13 +330,21 @@ LW Load word
LWL Load word left
LWR Load word right
// DIVU Divide unsigned
// DIV Divide
//MFHI Move from Hi
//MFLO Move from lo
//MTHI Move to HI
//MTLO Move to LO
//MULT Multiply
//MULT Multiply**
//MULTU Multiply unsigned
//MULTU Multiply unsigned**
//OR Bitwise or
@ -344,11 +352,11 @@ LWR Load word right
//SB Store byte
//SH Store half-word
//SH Store half-word**
//SLL Shift left logical
//SLLV Shift left logical variable
//SLLV Shift left logical variable **
//SLT Set on less than (signed)
@ -360,11 +368,11 @@ LWR Load word right
//SRA Shift right arithmetic
//SRAV Shift right arithmetic
//SRAV Shift right arithmetic**
//SRL Shift right logical
//SRLV Shift right logical variable
//SRLV Shift right logical variable**
//SUBU Subtract unsigned

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inputs/sb.txt Normal file
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@ -0,0 +1,4 @@
34040405
34050001
a0a40001
00000008

0
inputs/sh.txt Normal file
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