diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v
index ca117dd..c120971 100644
--- a/rtl/mips_cpu_bus.v
+++ b/rtl/mips_cpu_bus.v
@@ -30,6 +30,7 @@ logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly
 logic partial_write; // flag to control datapath when doing a partial write
 logic[31:0] partial_writedata; // modified data for partial writes (StoreHalfword or StoreByte)
 logic[31:0] write_data_address; // modified data address for partial writes
+logic clk_enable; // unused floating wire
 
 initial begin
     clk_internal = 1'b0;
@@ -44,6 +45,11 @@ initial begin
     clk_state = 0;
 end
 
+always_ff @(negedge reset) begin // kickstart clock after reset
+    clk_internal <= 1'b1;
+    state <= 2'b00;
+end
+
 always_ff @(posedge clk) begin // CLK Rising Edge
     if (!waitrequest && !clk_state) begin
         case (n_state)
@@ -212,7 +218,7 @@ mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper
 .reset(reset), // CPU reset, input
 .active(active), // Is CPU active, output
 .register_v0(register_v0), // $2 / $v0 debug bus, output
-.clk_enable(1'b0), // unused clock enable, input
+.clk_enable(clk_enable), // unused clock enable, input
 .instr_address(harvard_instr_address), // instr addr from pc, output
 .instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input
 .data_address(harvard_data_address), // harvard data memory address, output