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Mask address during partial writes
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50b9dba651
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@ -29,6 +29,7 @@ logic[3:0] write_byteenable; // byteenable calculator for partial write
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logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly
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logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly
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logic partial_write; // flag to control datapath when doing a partial write
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logic partial_write; // flag to control datapath when doing a partial write
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logic[31:0] partial_writedata; // modified data for partial writes (StoreHalfword or StoreByte)
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logic[31:0] partial_writedata; // modified data for partial writes (StoreHalfword or StoreByte)
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logic[31:0] write_data_address; // modified data address for partial writes
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initial begin
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initial begin
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clk_internal = 1'b0;
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clk_internal = 1'b0;
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@ -93,18 +94,22 @@ always_comb begin
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2'b00: begin
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2'b00: begin
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partial_writedata = {24{1'b0}, harvard_writedata[7:0]};
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partial_writedata = {24{1'b0}, harvard_writedata[7:0]};
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write_byteenable = 4'b0001;
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write_byteenable = 4'b0001;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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end
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2'b01: begin
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2'b01: begin
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partial_writedata = {16{1'b0}, harvard_writedata[7:0], 8{1'b0}};
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partial_writedata = {16{1'b0}, harvard_writedata[7:0], 8{1'b0}};
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write_byteenable = 4'b0010;
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write_byteenable = 4'b0010;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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end
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2'b10: begin
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2'b10: begin
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partial_writedata = {8{1'b0}, harvard_writedata[7:0], 16{1'b0}};
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partial_writedata = {8{1'b0}, harvard_writedata[7:0], 16{1'b0}};
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write_byteenable = 4'b0100;
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write_byteenable = 4'b0100;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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end
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2'b11: begin
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2'b11: begin
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partial_writedata = {harvard_writedata[7:0], 24{1'b0}};
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partial_writedata = {harvard_writedata[7:0], 24{1'b0}};
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write_byteenable = 4'b1000;
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write_byteenable = 4'b1000;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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end
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endcase
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endcase
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end
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end
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@ -114,18 +119,22 @@ always_comb begin
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2'b00: begin
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2'b00: begin
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partial_writedata = {16{1'b0}, harvard_writedata[15:0]};
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partial_writedata = {16{1'b0}, harvard_writedata[15:0]};
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write_byteenable = 4'b0011;
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write_byteenable = 4'b0011;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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end
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2'b01: begin // halfword address must be matrually aligned, last bit must be 0
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2'b01: begin // halfword address must be matrually aligned, last bit must be 0
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partial_writedata = 32'hxxxxxxxx;
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partial_writedata = 32'hxxxxxxxx;
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write_byteenable = 4'bxxxx;
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write_byteenable = 4'bxxxx;
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write_data_address = 32'hxxxxxxxx;
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end
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end
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2'b10: begin
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2'b10: begin
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partial_writedata = {harvard_writedata[15:0], 16{1'b0}};
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partial_writedata = {harvard_writedata[15:0], 16{1'b0}};
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write_byteenable = 4'b1100;
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write_byteenable = 4'b1100;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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end
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2'b11: begin // halfword address must be matrually aligned, last bit must be 0
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2'b11: begin // halfword address must be matrually aligned, last bit must be 0
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partial_writedata = 32'hxxxxxxxx;
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partial_writedata = 32'hxxxxxxxx;
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write_byteenable = 4'bxxxx;
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write_byteenable = 4'bxxxx;
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write_data_address = 32'hxxxxxxxx;
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end
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end
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endcase
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endcase
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end
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end
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@ -133,6 +142,7 @@ always_comb begin
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partial_write = 1'b0;
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partial_write = 1'b0;
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partial_writedata = 32'h00000000;
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partial_writedata = 32'h00000000;
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write_byteenable = 4'b1111;
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write_byteenable = 4'b1111;
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write_data_address = harvard_data_address;
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end
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end
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endcase
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endcase
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end
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end
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@ -184,7 +194,7 @@ always_comb begin
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n_state = 2'b00;
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n_state = 2'b00;
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end
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end
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2'b11: begin // connecting wires when in write state
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2'b11: begin // connecting wires when in write state
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address = harvard_data_address;
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address = write_data_address;
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read = 1'b0;
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read = 1'b0;
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write = 1'b1;
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write = 1'b1;
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byteenable = write_byteenable;
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byteenable = write_byteenable;
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