Update mips_cpu_memory.v

This commit is contained in:
jl7719 2020-12-02 23:41:04 +09:00
parent 64b9d16776
commit 10af46a352

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@ -5,13 +5,6 @@ Memory for Harvard Interface
- combinatorial read/fetch of instruction via instr_ port
- combinatorial read and single cycle write of data via data_ port
Constraints
read write
0 0 -> nothing
0 1 -> write
1 0 -> read
1 1 -> read ????? probs should never occur?
Instantiation of Memory Module
- mips_cpu_memory #(RAM_INIT_FILE) ramInst(clk, data_address, data_write, data_read, data_writedata, data_readdata, instr_address, instr_readdata);
@ -19,15 +12,10 @@ Special Memory Locations
- Whether a particular address maps to RAM, ROM, or something else is entirely down to the top-level circuit outside your CPU.
- special memory locations: 0x00000000 (CPU halt), 0xBFC00000 (start execution after reset)
- PC should be 0xBFC00000 at the start and 0x00000000 at the end
Needs checking with:
-- clk or clk_enable?
-- constraint on not being able to read and write in the same cycle
-- whether there is a more efficient way of initialising memory to zero (line 32)
*/
module mips_cpu_memory(
input logic clk_enable,
input logic clk,
//Data Memory
input logic[31:0] data_address,
@ -59,7 +47,7 @@ module mips_cpu_memory(
end
//Combinatorial read path for data and instruction.
if (clk_enable == 1) begin
if (clk == 1) begin
assign data_readdata = data_read ? memory[data_address] : 16'hxxxx;
assign instr_readdata = memory[instr_address];
end
@ -70,7 +58,7 @@ module mips_cpu_memory(
//Synchronous write path
always_ff @(posedge clk_enable) begin
always_ff @(posedge clk) begin
//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
if (instr_address != data_address) begin //cannot modify the instruction being read