diff --git a/inputs/sra/sra-1.ref.txt b/inputs/sra/sra-1.ref.txt
index dff79fe..46d53b5 100644
--- a/inputs/sra/sra-1.ref.txt
+++ b/inputs/sra/sra-1.ref.txt
@@ -1 +1 @@
-4294967040
\ No newline at end of file
+4227858432
\ No newline at end of file
diff --git a/inputs/sra/sra-1.txt b/inputs/sra/sra-1.txt
index 3a16f78..1cb5924 100644
--- a/inputs/sra/sra-1.txt
+++ b/inputs/sra/sra-1.txt
@@ -1,3 +1,3 @@
-3404F000
-00041103
+3C05F000
+00051083
 00000008
diff --git a/inputs/srav/srav-1.ref.txt b/inputs/srav/srav-1.ref.txt
index dff79fe..46d53b5 100644
--- a/inputs/srav/srav-1.ref.txt
+++ b/inputs/srav/srav-1.ref.txt
@@ -1 +1 @@
-4294967040
\ No newline at end of file
+4227858432
\ No newline at end of file
diff --git a/inputs/srav/srav-1.txt b/inputs/srav/srav-1.txt
index 1a39374..3b638bc 100644
--- a/inputs/srav/srav-1.txt
+++ b/inputs/srav/srav-1.txt
@@ -1,4 +1,4 @@
 34040004
-3405F000
+3C05F000
 00851007
-00000008
\ No newline at end of file
+00000008
diff --git a/inputs/sw/sw-1.ref.txt b/inputs/sw/sw-1.ref.txt
index b7bf491..35ff949 100644
--- a/inputs/sw/sw-1.ref.txt
+++ b/inputs/sw/sw-1.ref.txt
@@ -1 +1 @@
-4294967295
\ No newline at end of file
+65535
\ No newline at end of file
diff --git a/inputs/sw/sw-1.txt b/inputs/sw/sw-1.txt
index 6e0bac8..75b14c8 100644
--- a/inputs/sw/sw-1.txt
+++ b/inputs/sw/sw-1.txt
@@ -1,5 +1,5 @@
 3404FFFF
 34051008
 ACA40000
-8CA20000
+8CA20004
 00000008
\ No newline at end of file
diff --git a/reference.txt b/reference.txt
index 3440da4..bf33fcf 100644
--- a/reference.txt
+++ b/reference.txt
@@ -720,31 +720,31 @@ jr $0
 
 register_v0 = 0
 
-#==SRA	Shift right arithmetic==
+==SRA	Shift right arithmetic==
 
-ori $4,$0,2
-sra $2,$4,1
-jr $0
+lui $5 $0,0xF000
+srav $2,$5,2
+jr $0    
 
-34040001
-00041043
+3C05F000
+00051083
 00000008
 
-register_v0 = 1
+register_v0 = 0xFC000000
 
-==SRAV	Shift right arithmetic==
+==SRAV	Shift right arithmetic variable==
 
 ori $4,$0,2
-ori $5 $0,1
+lui $5 $0,0xF000
 srav $2,$5,$4
 jr $0    
 
-34040002
-34050001
+34040004
+3C05F000
 00851007
 00000008
 
-register_v0 = 1
+register_v0 = 0xFC000000
 
 ==SRL	Shift right logical==
 
@@ -756,7 +756,7 @@ jr $0
 00041082
 00000008
 
-register_v0 = 3
+register_v0 = 4
 
 ==SRLV	Shift right logical variable==
 
@@ -770,7 +770,7 @@ jr $0
 00851006
 00000008
 
-register_v0 = 3
+register_v0 = 4
 
 ==SUBU	Subtract unsigned==
 
@@ -790,16 +790,14 @@ register_v0 = 2
 
 ori $4, $0, 0xFFFF  
 ori $5, $0, 0x1008  
-sw $4, 4($5)        
-ori $5, $0, 0x100C   
-lw $2, 0($5)       
+sw $4, 4($5)         
+lw $2, 4($5)       
 jr $0               
 
 3404FFFF
 34051008
 ACA40004
-3405100C
-8CA20000
+8CA20004
 00000008
 
 register_v0 = 0x0000FFFF
@@ -821,7 +819,7 @@ register_v0 = 7
 ==XORI	Bitwise exclusive or immediate==
 
 ori $4,$0,5
-xori $2,$4,0xF
+xori $2,$4,0x000F
 jr $0
 
 34040005