From 04b1ed4fed542d3b4b81a5cf6a2b887edbc96e29 Mon Sep 17 00:00:00 2001 From: jl7719 Date: Thu, 10 Dec 2020 22:27:08 +0900 Subject: [PATCH] Update control and memory Fixed some errors when testing --- rtl/mips_cpu_control.v | 17 ++++++++--------- rtl/mips_cpu_memory.v | 2 +- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v index f51c723..28198d1 100644 --- a/rtl/mips_cpu_control.v +++ b/rtl/mips_cpu_control.v @@ -83,9 +83,9 @@ assign rt = Instr[20:16]; always @(*) begin //CtrlRegDst logic - if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI))begin // + if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI))begin CtrlRegDst = 2'd0; //Write address comes from rt - end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin// + end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin CtrlRegDst = 2'd1; //Write address comes from rd end else if (op == JAL)begin CtrlRegDst = 2'd2; //const reg 31, for writing to the link register @@ -96,10 +96,10 @@ always @(*) begin CtrlPC = 2'd1; // Branches - Jumps relative to PC end else if((op==J) || (op==JAL))begin CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction - end else if((op==JR) || (op==JALR))begin + end else if((funct==JR) || (funct==JALR))begin CtrlPC = 2'd3; // Jumps using Register. - $display("Ctrl PC Jump Register"); - end else begin CtrlPC = 2'd0; $display("Ctrl PC No Jump/Branch");end // No jumps or branches, just increment to next word + //$display("Ctrl PC Jump Register"); + end else begin CtrlPC = 2'd0; /*/$display("Ctrl PC No Jump/Branch");*/end // No jumps or branches, just increment to next word //CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled. if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR))begin @@ -115,7 +115,7 @@ always @(*) begin //CtrlALUOp Logic if((op==ADDIU) || ((op==SPECIAL)&&(funct==ADDU)))begin CtrlALUOp = 5'd0; //ADD from ALUOps - end else if((op==ANDI) || ((op==SPECIAL)&&(funct==AND)))begin((op==ANDI) || ((op==SPECIAL)&&(funct==AND))) + end else if((op==ANDI) || ((op==SPECIAL)&&(funct==AND)))begin CtrlALUOp = 5'd4;//AND from ALUOps end else if(op==BEQ) begin CtrlALUOp = 5'd13;//EQ from ALUOps @@ -133,7 +133,7 @@ always @(*) begin CtrlALUOp = 5'd3;//DIV from ALUOps end else if((op==SPECIAL)&&(funct==DIVU))begin CtrlALUOp = 5'd23;//DIVU from ALUOps - end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SBH) || (op==SW))begin + end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin CtrlALUOp = 5'd0;//ADD from ALUOps end else if(op==LUI)begin CtrlALUOp = 5'd7;//SLL from ALUOps @@ -189,9 +189,8 @@ always @(*) begin end else begin CtrlALUSrc = 1'bx;end //CtrlRegWrite logic - if((op == ADDIU | op == ANDI | op == LB | op == LBU | op == LH | op == LHU | op == LUI | op == LW | op == LWL | op == LWR | op == ORI | op == SLTI | op == SLTIU | op == XORI | (op == SPECIAL & ((funct == ADDU | funct == AND | funct == DIV | funct == DIVU | funct == MULT | funct == MULTU | funct == JALR | funct == OR | funct == SLL | funct == SLLV | funct == SLT | funct == SLTU | funct == SRA | funct == SRAV | funct == SRL | funct == SRLV | funct == SUBU | funct == XOR)))))begin + if ((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) begin CtrlRegWrite = 1;//The Registers are Write Enabled end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled - ((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) end endmodule diff --git a/rtl/mips_cpu_memory.v b/rtl/mips_cpu_memory.v index ee7544e..b87312c 100644 --- a/rtl/mips_cpu_memory.v +++ b/rtl/mips_cpu_memory.v @@ -49,7 +49,7 @@ module mips_cpu_memory( //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]); if (!data_read & data_write) begin //cannot read and write to memory in the same cycle if (instr_address != data_address) begin //cannot modify the instruction being read - data_memory[data_address] <= data_writedata; + data_memory[data_address>>2] <= data_writedata; end end end