mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-12-23 05:45:47 +00:00
368 lines
8.3 KiB
Coq
368 lines
8.3 KiB
Coq
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/*
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Instr
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*0: XOR SUBU SRLV SRL SRAV SRA SLTU SLT SLLV
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SLL OR MULTU MULT MTLO MTHI JR JALR DIVU
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DIV AND ADDU
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1: BLTZAL BLTZ BGEZAL BGEZ
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2: J
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3: JAL
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4: BEQ
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5: BNE
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6: BLEZ
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7: BGTZ
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*9: ADDIU
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10: SLTI
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11: SLTIU
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12: ANDI
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13: ORI
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14: XORI
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15: LUI
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32: LB
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33: LH
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34: LWL
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*35: LW
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36: LBU
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37: LHU
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38: LWR
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40: SB
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41: SH
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*43: SW
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*/
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/*
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Regdst:
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00:Instr[20-16]
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01:Instr[15-11]
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10:2'd31
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*/
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/*
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Memtoreg:
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00: Alu output
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01: Memory output
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10: PC+4 output
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*/
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/*
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Aluop:
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0: r-type instructions
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1: <0
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2: >=0
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3: =0
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4: =/=0
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5: <=0
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6: >0
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7: add
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8: slt (signed)
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9: slt (unsigned)
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10: and
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11: or
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12: xor
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*/
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//Commented signals represents dont care(x)
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module MIPS_Control_Harvard(
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input logic[5:0] Instr,
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input logic[5:0] Instr2,
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output logic[1:0] Regdst,
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output logic Branch,
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output logic Memread,
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output logic[1:0] Memtoreg,
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output logic[3:0] Aluop,
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output logic Memwrite,
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output logic Alusrc,
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output logic Regwrite,
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output logic Jump,
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);
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always_comb begin
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case(Instr)
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6'd0: begin
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Regdst=2'b01;
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Branch=0;
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Memread=0;
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Memwrite=0;
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Memtoreg=2'b00;
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Aluop=4'd0;
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Alusrc=0;
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Regwrite=1;
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Jump=0;
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end
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6'd1: begin
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Regdst=2'b10;
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Branch=1;
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Memread=0;
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Memwrite=0;
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if(Instr2[5]==1)begin
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Memtoreg=2'b10;
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Regwrite=1;
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end
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if (Instr2[0]==0)begin
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Aluop=4'd1;
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end
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if (Instr2[0]==1)begin
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Aluop=4'd2;
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end
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Alusrc=0;
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Jump=0;
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end
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6'd2: begin
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//Regdst=2'b;
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Branch=0;
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Memread=0;
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//Memtoreg=;
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//Aluop=4'd;
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Memwrite=0;
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//Alusrc=;
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Regwrite=0;
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Jump=1;
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end
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6'd3: begin
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Regdst=2'b10;
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Branch=0;
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Memread=0;
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Memtoreg=2'b10;
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//aluop=4'd;
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Memwrite=0;
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//Alusrc=;
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Regwrite=1;
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Jump=1;
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end
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6'd4: begin
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//Regdst=2'b;
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd3;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0;
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Jump=0;
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end
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6'd5: begin
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//Regdst=2'b;
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd4;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0
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Jump=0;
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end
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6'd6: begin
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//Regdst=2'b;
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd5;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0;
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Jump=0;
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end
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6'd7: begin
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//Regdst=2'b;
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Branch=1;
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Memread=0;
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//Memtoreg=;
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Aluop4'd6;
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Memwrite=0;
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Alusrc=0;
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Regwrite=0;
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Jump=0;
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end
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6'd9: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd10: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd8;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd11: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd9;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd12: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd10;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd13: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd11;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd14: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2'b00;
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Aluop=4'd12;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd15: begin
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Regdst=2'b00;
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Branch=0;
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Memread=0;
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Memtoreg=2b'00;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd32: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd33: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd8;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd34: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd35: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd36: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd37: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd38: begin
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Regdst=2'b00;
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Branch=0;
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Memread=1;
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Memtoreg=2'b01;
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Aluop=4'd7;
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Memwrite=0;
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Alusrc=1;
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Regwrite=1;
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Jump=0;
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end
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6'd40: begin
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//Regdst=2'b;
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Branch=0;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd7;
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Memwrite=1;
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Alusrc=1;
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Regwrite=0;
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Jump=0;
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end
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6'd41: begin
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//Regdst=2'b;
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Branch=0;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd7;
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Memwrite=1;
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Alusrc=1;
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Regwrite=0;
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Jump=0;
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end
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6'd43: begin
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//Regdst=2'b;
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Branch=0;
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Memread=0;
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//Memtoreg=;
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Aluop=4'd7;
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Memwrite=1;
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Alusrc=1;
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Regwrite=0;
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Jump=0;
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end
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endcase
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end
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endmodule
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