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21 lines
602 B
Coq
21 lines
602 B
Coq
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module mips_cpu_harvard(
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/* Standard signals */
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input logic clk,
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input logic reset,
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output logic active,
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output logic [31:0] register_v0,
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/* New clock enable. See below. */
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input logic clk_enable,
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/* Combinatorial read access to instructions */
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output logic[31:0] instr_address,
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input logic[31:0] instr_readdata,
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/* Combinatorial read and single-cycle write access to instructions */
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output logic[31:0] data_address,
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output logic data_write,
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output logic data_read,
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output logic[31:0] data_writedata,
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input logic[31:0] data_readdata
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);
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