ELEC50010-IAC-CW/rtl/mips_cpu_pc.v

27 lines
379 B
Coq
Raw Normal View History

module pc(
input logic clk,
input logic rst,
input logic[31:0] pc_in,
output logic[31:0] pc_out
);
reg[31:0] pc_curr;
initial begin
pc_curr = 32'hBFC00000;
end // initial
always_comb begin
if (rst) begin
pc_curr = 32'hBFC00000;
end else begin
pc_curr = pc_in;
2020-11-30 12:08:58 +00:00
end
end
2020-11-30 12:08:58 +00:00
always_ff @(posedge clk) begin
pc_out <= pc_curr;
end
2020-11-30 12:08:58 +00:00
endmodule // pc