mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-09-19 19:46:17 +00:00
122 lines
3.9 KiB
Plaintext
122 lines
3.9 KiB
Plaintext
|
/*
|
||
|
WARNING: Do NOT edit the input and output ports in this file in a text
|
||
|
editor if you plan to continue editing the block that represents it in
|
||
|
the Block Editor! File corruption is VERY likely to occur.
|
||
|
*/
|
||
|
/*
|
||
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||
|
Your use of Intel Corporation's design tools, logic functions
|
||
|
and other software and tools, and any partner logic
|
||
|
functions, and any output files from any of the foregoing
|
||
|
(including device programming or simulation files), and any
|
||
|
associated documentation or information are expressly subject
|
||
|
to the terms and conditions of the Intel Program License
|
||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||
|
agreement, including, without limitation, that your use is for
|
||
|
the sole purpose of programming logic devices manufactured by
|
||
|
Intel and sold by Intel or its authorized distributors. Please
|
||
|
refer to the applicable agreement for further details, at
|
||
|
https://fpgasoftware.intel.com/eula.
|
||
|
*/
|
||
|
(header "symbol" (version "1.2"))
|
||
|
(symbol
|
||
|
(rect 16 16 240 208)
|
||
|
(text "ALU" (rect 5 0 21 10)(font "Tahoma" (font_size 6)))
|
||
|
(text "inst" (rect 8 171 24 188)(font "Intel Clear" ))
|
||
|
(port
|
||
|
(pt 0 32)
|
||
|
(input)
|
||
|
(text "clk" (rect 0 0 16 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "clk" (rect 21 27 37 46)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 0 32)(pt 16 32))
|
||
|
)
|
||
|
(port
|
||
|
(pt 0 48)
|
||
|
(input)
|
||
|
(text "rst" (rect 0 0 15 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "rst" (rect 21 43 36 62)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 0 48)(pt 16 48))
|
||
|
)
|
||
|
(port
|
||
|
(pt 0 64)
|
||
|
(input)
|
||
|
(text "A[31:0]" (rect 0 0 44 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "A[31:0]" (rect 21 59 65 78)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 0 64)(pt 16 64))
|
||
|
)
|
||
|
(port
|
||
|
(pt 0 80)
|
||
|
(input)
|
||
|
(text "B[31:0]" (rect 0 0 44 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "B[31:0]" (rect 21 75 65 94)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 0 80)(pt 16 80))
|
||
|
)
|
||
|
(port
|
||
|
(pt 0 96)
|
||
|
(input)
|
||
|
(text "ALUOp[4:0]" (rect 0 0 70 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "ALUOp[4:0]" (rect 21 91 91 110)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 0 96)(pt 16 96))
|
||
|
)
|
||
|
(port
|
||
|
(pt 0 112)
|
||
|
(input)
|
||
|
(text "shamt[4:0]" (rect 0 0 64 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "shamt[4:0]" (rect 21 107 85 126)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 0 112)(pt 16 112))
|
||
|
)
|
||
|
(port
|
||
|
(pt 0 128)
|
||
|
(input)
|
||
|
(text "Hi_in[31:0]" (rect 0 0 67 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "Hi_in[31:0]" (rect 21 123 88 142)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 0 128)(pt 16 128))
|
||
|
)
|
||
|
(port
|
||
|
(pt 0 144)
|
||
|
(input)
|
||
|
(text "Lo_in[31:0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "Lo_in[31:0]" (rect 21 139 89 158)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 0 144)(pt 16 144))
|
||
|
)
|
||
|
(port
|
||
|
(pt 0 160)
|
||
|
(input)
|
||
|
(text "SpcRegWriteEn" (rect 0 0 90 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "SpcRegWriteEn" (rect 21 155 111 174)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 0 160)(pt 16 160))
|
||
|
)
|
||
|
(port
|
||
|
(pt 224 32)
|
||
|
(output)
|
||
|
(text "ALUCond" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "ALUCond" (rect 148 27 203 46)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 224 32)(pt 208 32))
|
||
|
)
|
||
|
(port
|
||
|
(pt 224 48)
|
||
|
(output)
|
||
|
(text "ALURes[31:0]" (rect 0 0 82 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "ALURes[31:0]" (rect 121 43 203 62)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 224 48)(pt 208 48))
|
||
|
)
|
||
|
(port
|
||
|
(pt 224 64)
|
||
|
(output)
|
||
|
(text "ALUHi[31:0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "ALUHi[31:0]" (rect 129 59 203 78)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 224 64)(pt 208 64))
|
||
|
)
|
||
|
(port
|
||
|
(pt 224 80)
|
||
|
(output)
|
||
|
(text "ALULo[31:0]" (rect 0 0 75 19)(font "Intel Clear" (font_size 8)))
|
||
|
(text "ALULo[31:0]" (rect 128 75 203 94)(font "Intel Clear" (font_size 8)))
|
||
|
(line (pt 224 80)(pt 208 80))
|
||
|
)
|
||
|
(drawing
|
||
|
(rectangle (rect 16 16 208 176))
|
||
|
)
|
||
|
)
|