ELEC50003-P1-CW/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.cmp

50 lines
4.9 KiB
Plaintext

component Qsys is
port (
alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(23 downto 0); -- vid_data
alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
alt_vip_itc_0_clocked_video_vid_v : out std_logic; -- vid_v
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
clk_sdram_clk : out std_logic; -- clk
clk_vga_clk : out std_logic; -- clk
d8m_xclkin_clk : out std_logic; -- clk
eee_imgproc_0_conduit_mode_new_signal : in std_logic := 'X'; -- new_signal
i2c_opencores_camera_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
i2c_opencores_camera_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
i2c_opencores_mipi_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
i2c_opencores_mipi_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
key_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
led_external_connection_export : out std_logic_vector(9 downto 0); -- export
mipi_pwdn_n_external_connection_export : out std_logic; -- export
mipi_reset_n_external_connection_export : out std_logic; -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
terasic_auto_focus_0_conduit_vcm_i2c_sda : inout std_logic := 'X'; -- vcm_i2c_sda
terasic_auto_focus_0_conduit_clk50 : in std_logic := 'X'; -- clk50
terasic_auto_focus_0_conduit_vcm_i2c_scl : inout std_logic := 'X'; -- vcm_i2c_scl
terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D
terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL
terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL
terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X'; -- PIXCLK
uart_0_rx_tx_rxd : in std_logic := 'X'; -- rxd
uart_0_rx_tx_txd : out std_logic -- txd
);
end component Qsys;