ELEC50003-P1-CW/Vision/DE10_LITE_D8M_VIP_16/uart_interface_hw.tcl
2021-05-28 00:40:25 +01:00

116 lines
3.3 KiB
Tcl

# TCL File Generated by Component Editor 16.1
# Thu May 27 17:12:45 BST 2021
# DO NOT MODIFY
#
# uart_interface "uart_interface" v1.0
# 2021.05.27.17:12:45
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module uart_interface
#
set_module_property DESCRIPTION ""
set_module_property NAME uart_interface
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME uart_interface
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL uart
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file uart.v VERILOG PATH ip/de10lite-hdl/uart.v TOP_LEVEL_FILE
#
# parameters
#
add_parameter CLK_FREQ INTEGER 50000000
set_parameter_property CLK_FREQ DEFAULT_VALUE 50000000
set_parameter_property CLK_FREQ DISPLAY_NAME CLK_FREQ
set_parameter_property CLK_FREQ TYPE INTEGER
set_parameter_property CLK_FREQ UNITS None
set_parameter_property CLK_FREQ HDL_PARAMETER true
add_parameter BAUD INTEGER 115200
set_parameter_property BAUD DEFAULT_VALUE 115200
set_parameter_property BAUD DISPLAY_NAME BAUD
set_parameter_property BAUD TYPE INTEGER
set_parameter_property BAUD UNITS None
set_parameter_property BAUD HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock clock
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end rx rx Input 1
add_interface_port conduit_end rx_data rx_data Output 8
add_interface_port conduit_end rx_valid rx_valid Output 1
add_interface_port conduit_end tx tx Output 1
add_interface_port conduit_end tx_data tx_data Input 8
add_interface_port conduit_end tx_transmit tx_transmit Input 1
add_interface_port conduit_end tx_ready tx_ready Output 1