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ELEC50003-P1-CW/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt
anishghanekar d0619cd9cd Changed Colour recognition code
2021-05-28 00:40:25 +01:00

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Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --block-symbol-file --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys" --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
Progress: Parameterizing module TERASIC_CAMERA_0
Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.1]
Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.1]
Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1]
Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.1]
Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.1]
Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1]
Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1]
Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1]
Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.1]
Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1]
Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.1]
Progress: Parameterizing module timer
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --synthesis=VERILOG --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys\synthesis" --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
Progress: Parameterizing module TERASIC_CAMERA_0
Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.1]
Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.1]
Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1]
Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.1]
Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.1]
Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1]
Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1]
Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1]
Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.1]
Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1]
Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.1]
Progress: Parameterizing module timer
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH
Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
Info: Inserting clock-crossing logic between cmd_demux.src14 and cmd_mux_014.sink0
Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
Info: Inserting clock-crossing logic between rsp_demux_014.src0 and rsp_mux.sink14
Info: EEE_IMGPROC_0: "Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0"
Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"
Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"
Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0"
Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"
Info: altpll_0: "Qsys" instantiated altpll "altpll_0"
Info: i2c_opencores_camera: "Qsys" instantiated i2c_opencores "i2c_opencores_camera"
Info: jtag_uart: Starting RTL generation for module 'Qsys_jtag_uart'
Info: jtag_uart: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ]
Info: jtag_uart: Done RTL generation for module 'Qsys_jtag_uart'
Info: jtag_uart: "Qsys" instantiated altera_avalon_jtag_uart "jtag_uart"
Info: key: Starting RTL generation for module 'Qsys_key'
Info: key: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ]
Info: key: Done RTL generation for module 'Qsys_key'
Info: key: "Qsys" instantiated altera_avalon_pio "key"
Info: led: Starting RTL generation for module 'Qsys_led'
Info: led: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ]
Info: led: Done RTL generation for module 'Qsys_led'
Info: led: "Qsys" instantiated altera_avalon_pio "led"
Info: mipi_pwdn_n: Starting RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ]
Info: mipi_pwdn_n: Done RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: "Qsys" instantiated altera_avalon_pio "mipi_pwdn_n"
Info: nios2_gen2: "Qsys" instantiated altera_nios2_gen2 "nios2_gen2"
Info: onchip_memory2_0: Starting RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ]
Info: onchip_memory2_0: Done RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: "Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"
Info: sdram: Starting RTL generation for module 'Qsys_sdram'
Info: sdram: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ]
Info: sdram: Done RTL generation for module 'Qsys_sdram'
Info: sdram: "Qsys" instantiated altera_avalon_new_sdram_controller "sdram"
Info: sw: Starting RTL generation for module 'Qsys_sw'
Info: sw: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ]
Info: sw: Done RTL generation for module 'Qsys_sw'
Info: sw: "Qsys" instantiated altera_avalon_pio "sw"
Info: sysid_qsys: "Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys"
Info: timer: Starting RTL generation for module 'Qsys_timer'
Info: timer: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ]
Info: timer: Done RTL generation for module 'Qsys_timer'
Info: timer: "Qsys" instantiated altera_avalon_timer "timer"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_1: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: irq_mapper: "Qsys" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "Qsys" instantiated altera_reset_controller "rst_controller"
Info: vfb_writer_packet_write_address_au_l_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"
Info: vfb_writer_packet_write_address_au: "alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"
Info: vfb_writer_overflow_flag_reg: "alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: vfb_writer_length_counter_au_enable_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"
Info: din: "alt_vip_vfb_0" instantiated alt_avalon_st_input "din"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: dout: "alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master: "alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master_pull: "alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: write_master_push: "alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: pc0: "alt_vip_vfb_0" instantiated alt_pc "pc0"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: fu_id_4494_line325_93: "alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: clocksource: "alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: cpu: Starting RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ]
Info: cpu: # 2021.05.27 17:51:00 (*) Starting Nios II generation
Info: cpu: # 2021.05.27 17:51:00 (*) Checking for plaintext license.
Info: cpu: # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:51:01 (*) Plaintext license not found.
Info: cpu: # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation).
Info: cpu: # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF)
Info: cpu: # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings
Info: cpu: # 2021.05.27 17:51:01 (*) Creating all objects for CPU
Info: cpu: # 2021.05.27 17:51:01 (*) Testbench
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction decoding
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction fields
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction decodes
Info: cpu: # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction controls
Info: cpu: # 2021.05.27 17:51:02 (*) Pipeline frontend
Info: cpu: # 2021.05.27 17:51:02 (*) Pipeline backend
Info: cpu: # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects
Info: cpu: # 2021.05.27 17:51:06 (*) Creating encrypted RTL
Info: cpu: # 2021.05.27 17:51:07 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: "nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"
Info: nios2_gen2_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"
Info: jtag_uart_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"
Info: nios2_gen2_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"
Info: jtag_uart_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"
Info: jtag_uart_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_006: "mm_interconnect_0" instantiated altera_merlin_router "router_006"
Info: nios2_gen2_data_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: cmd_mux_004: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_demux_004: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"
Info: rsp_demux_005: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002"
Info: sdram_s1_burst_adapter: "mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: sdram_s1_rsp_width_adapter: "mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: avalon_st_adapter: "mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: Qsys: Done "Qsys" with 67 modules, 142 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
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